
Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r
DS2180A041995 10/36TRANSMIT INSERTION HIERARCHY Figure 8F-BITIDLECLEARSIGB7 STUFFTSERTSERTSERTSERNTSER193S YELLOW ALARM – B2 STUFFB7 STUFFTSER + ABCD
DS2180A041995 11/36193S TRANSMIT MULTIFRAME TIMING Figure 9TLCLK123 4567891011121 23 45612BABAFRAME #TFSYNCTMSYNC1TMO1TSIGSELTABCD2TLINK3TSIGFRNOTES:
DS2180A041995 12/36193E TRANSMIT MULTIFRAME TIMING Figure 10TLCLK1 2 3 4 5 6 7 8 9 1011 12131415 16171824DABCFRAME #TFSYNCTMSYNC1TMO1TSIGSELTABCD2TLI
DS2180A041995 13/36TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11LSB MSB LSB MSBF LSB MSBLSB MSB LSB MSB LSB MSBFTCLKTMSYNCTMOTFSYNCTSIGSELTSIGFRTLCLK
DS2180A041995 14/36RECEIVE CONTROL REGISTER Figure 12(MSB) (LSB)ARC OOF RCI RCS SYNCC SYNCT SYNCE RESYNCSYMBOL POSITION NAME AND DESCRIPTIONARC RCR.7
DS2180A041995 15/36RECEIVE SIGNALINGRobbed bit signaling data is presented at RABCD dur-ing each channel time in signaling frames for all 24 in-coming
DS2180A041995 16/36193E RECEIVE MULTIFRAME TIMING Figure 151 2 3 4 5 6 7 8 91011121314 151617FRAME#RFSYNCRMSYNCRSIGSELRSIGFRRLCLKRABCD1RLINK218 19 20
DS2180A041995 17/36RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16LSB MSB LSB MSBF LSB MSBLSB MSBLSB MSBF LSB MSBCHANNEL 24 B OR DCHANNEL 23 B OR DRCLKR
DS2180A041995 18/36RSR: RECEIVE STATUS REGISTER Figure 17(MSB) (LSB)BVCS ECS RYEL RCL FERR B8ZSD RBL RLOSSYMBOL POSITION NAME AND DESCRIPTIONBVCS RSR.
DS2180A041995 19/36RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18(MSB) (LSB)BVCS ECS RYEL RCL FERR B8ZSD RBL RLOSSYMBOL POSITION NAME AND DESCRIPTION
TransmitTimingF-BitDataDataSelectorBipolarCoderYellowAlarmCRCSerialControlInterfaceYellowAlarmDetectInformationRegistersReceiveSyncControllerCodeGenDa
DS2180A041995 20/36BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19(MSB) (LSB)BVD7 BVD6 BVD5 BVD4 BVD3 BVD2 BVD1 BVD0SYMBOL POSITION NAME AND DESCRIPT
DS2180A041995 21/36RYEL OUTPUTThe yellow alarm output transitions high when a yellowalarm is detected. A high-low transition indicates thealarm condit
DS2180A041995 22/36HARDWARE MODEFor preliminary system prototyping or applicationswhich do not require the features offered by the serialport, the tra
DS2180A041995 23/36T1 OVERVIEWFraming StandardsThe DS2180A is compatible with the existing Bell Sys-tem D4 framing standard described in ATT PUB 43801
DS2180A041995 24/36193E FRAMING FORMAT Table 7FRAMEF-BIT USE BIT USE IN EACH CHANNEL SIGNALING-BIT USEFRAMENUMBERFPS1FDL2CRC3DATA SIGNALING 2STATE4ST
DS2180A041995 25/36193S FRAMING FORMAT Table 8FRAMENUMBERF-BIT USE BIT USE IN EACH CHANNELSIGNALING-BIT USENUMBERFT1FS2DATA SIGNALING4123456789101112
DS2180A041995 26/36TRANSMIT SIDE OVERVIEWThe transmit side of the DS2180A is made up of six ma-jor functional blocks: timing and clock generation, dat
DS2180A041995 27/36nizer before sync is declared. Clearing RCR.3 causesthe synchronizer to search for FT patterns (101010...)without cross-coupling th
DS2180A041995 28/36BACKPLANE INTERFACE USING DS2180A AND DS2176 Figure 22TRANSMITLINE INTERFACEDS2186RECEIVELINE INTERFACEDS2187TRANSMITBACKPLANEINTE
DS2180A041995 29/36PROCESSOR-BASED TRANSMIT SIGNALING INSERTION Figure 23SPSINTSDOSDISCLKCSTSIGFRTCHCLKTABCDTMSYNCTFSYNCINT1P1.1P1.0TXDRXDINT08031/51
DS2180A041995 3/36TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe Sync. May be pulsed hig
DS2180A041995 30/36ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to 7.0VOperating Temperature 0°C to +70°CStorage Temperature –
DS2180A041995 31/36AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESSDI to SCLK Setup tDC50 nsSCLK t
DS2180A041995 32/36SERIAL PORT READ AC TIMINGCSSCLKSDOtCDZHigh ZtCDVNOTE:1. Serial port write must precede a port read to provide address information.
DS2180A041995 33/36AC ELECTRICAL CHARACTERISTICS1 – RECEIVE (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESPropagation Delay RCL
DS2180A041995 34/36TRANSMIT AC TIMING DIAGRAMTCHCLK, TPOS,TNEGTFSYNC, TMSYNCTSER, TABCD,TLINKTCLKtSTDtHTDtWHtPtWLtFtRtSTStPTStPTCHTMO, TLCLK,TSIGSEL,
DS2180A041995 35/36DS2180A SERIAL T1 TRANSCEIVER (600 MIL DIP)BDACKG HJEF1INCHESDIM. MIN. MAX.A 2.050 2.075B 0.530 0.550C 0.140 0.160D 0.600 0.625E 0.
DS2180A041995 36/36DS2180AQ SERIAL T1 TRANSCEIVER (PLCC)CA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE
DS2180A041995 4/36POWER AND TEST PIN DESCRIPTION (40–PIN DIP ONLY) Table 3PIN SYMBOL TYPE DESCRIPTION20 VSS– Signal Ground. 0.0 volts.32 TEST I Test
DS2180A041995 5/36REGISTER SUMMARY Table 5REGISTER ADDRESS T/R1DESCRIPTION/FUNCTIONRSR 0000 R2Receive Status Register. Reports all receive alarm cond
DS2180A041995 6/36DATA I/OFollowing the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into theaddressed regist
DS2180A041995 7/36COMMON CONTROL REGISTER Figure 4(MSB) (LSB)– FRSR2 EYELMD FM SYELMD B8ZS B7 LPBKSYMBOL POSITION NAME AND DESCRIPTION– CCR.7 Reserved
DS2180A041995 8/36B8ZSThe DS2180A supports existing and emerging zerosuppression formats. Selection of B8ZS coding main-tains system 1’s density requi
DS2180A041995 9/36TRANSMIT SIGNALINGWhen enabled (via TCR.4) channel signaling is insertedin frames 6 and 12 (193S) or in frames 6, 12, 18 and 24(193E
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