Rainbow-electronics AT84AD001B Instrukcja Użytkownika

1 2153C–BDC–04/04Features• Dual ADC with 8-bit Resolution• 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode• Single or 1:2 Demultiplexed O

10AT84AD001B 2153C–BDC–04/04Note: One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration p

11 AT84AD001B 2153C–BDC–04/04Table 7. Switching PerformancesParameter Symbol Min Typ Max UnitSwitching Performance and Characteristics - See “Timing

12AT84AD001B 2153C–BDC–04/04Timing DiagramsFigure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC QFigure 5. 1

13 AT84AD001B 2153C–BDC–04/04Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC QCLKOI (= CLKI/4)CLKI CLKOI (= CLKI/2)VINTANN + 1N + 2N + 3Pipe

14AT84AD001B 2153C–BDC–04/04Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC QDOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impeda

15 AT84AD001B 2153C–BDC–04/04Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC QCLKI CLKOI (= CLKI/2)VINTANN + 1N + 4N + 6Pipeline delay = 4

16AT84AD001B 2153C–BDC–04/04Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC QFigure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)N

17 AT84AD001B 2153C–BDC–04/04Figure 11. Data Ready ResetFigure 12. Data Ready Reset 1:1 DMUX ModeNote: The Data Ready Reset is taken into account o

18AT84AD001B 2153C–BDC–04/04Figure 13. Data Ready Reset 1:2 DMUX ModeNotes: 1. In 1:2 DMUX, Fs/2 mode: The Data Ready Reset is taken into account on

19 AT84AD001B 2153C–BDC–04/04Functions DescriptionTable 8. Description of FunctionsName Function VCCAPositive analog power supplyVCCDPositive digit

2AT84AD001B 2153C–BDC–04/04Description The AT84AD001B is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and

20AT84AD001B 2153C–BDC–04/04Digital Output Coding (Nominal Settings)Pin DescriptionTable 9. Digital Output Coding (Nominal Setting) Differential Ana

21 AT84AD001B 2153C–BDC–04/04CLKQN 128Inverted phase (-) clock input signal (CLKQ)DDRB 126 Synchronous data ready reset I and QDDRBN 127 Inverted pha

22AT84AD001B 2153C–BDC–04/04Figure 14. AT84AD001B Pinout (Top View)CLKOIN 122 Inverted phase (-) output clock channel ICLKOQ 132Output clock in-pha

23 AT84AD001B 2153C–BDC–04/04Typical Characterization ResultsNominal conditions (unless otherwise specified):•VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V•

24AT84AD001B 2153C–BDC–04/04Typical Crosstalk Figure 16. Crosstalk (Fs = 500 Msps)Note: Measured on the AT84AD001TD-EB Evaluation Board.Typical DC,

25 AT84AD001B 2153C–BDC–04/04Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)Typical Step Response Figure 19. Step Response• Fs

26AT84AD001B 2153C–BDC–04/04Figure 20. Step Response (Zoom)• Fs = 1 Gsps• Pclock = 0 dBm• Fin = 500 MHz•Pin = -1 dBFSFigure 21. Step Response050100

27 AT84AD001B 2153C–BDC–04/04Figure 22. Step Response (Zoom)Typical Dynamic Performances Versus Sampling FrequencyFigure 23. ENOB Versus Sampling F

28AT84AD001B 2153C–BDC–04/04Figure 25. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)Figure 26. SNR Versus Sampling Frequency in

29 AT84AD001B 2153C–BDC–04/04Figure 28. SFDR Versus Input Frequency (Fs = 1 Gsps)Figure 29. THD Versus Input Frequency (Fs = 1 Gsps)Figure 30. SNR

3 AT84AD001B 2153C–BDC–04/04Figure 1. Simplified Block DiagramDOIRIDOIRINDOIRQDOIRQNCLKIClock BufferDivider2 to16DRDAILVDSClockBuffer2CLKIODDRB16DOA

30AT84AD001B 2153C–BDC–04/04Typical Reconstructed Signals and Signal SpectrumFigure 31. Fs = 1 Gsps and Fin = 20 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA

31 AT84AD001B 2153C–BDC–04/04Figure 34. Fs = 1 Gsps and Fin = 20 MHz (Interleaving Mode Fint = 2 Gsps, Fs/4 DR Type, FiSDA = -15 ps, ISA = -50 ps)Fi

32AT84AD001B 2153C–BDC–04/04Typical Performance Sensitivity Versus Power Supplies and TemperatureFigure 36. ENOB Versus VCCA = VCCD (Fs = 1 Gsps, Fi

33 AT84AD001B 2153C–BDC–04/04Figure 38. THD Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 39. SNR Ver

34AT84AD001B 2153C–BDC–04/04Figure 40. ENOB Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 41. SFDR Versus J

35 AT84AD001B 2153C–BDC–04/04Figure 42. THD Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 43. SNR Versus Ju

36AT84AD001B 2153C–BDC–04/04Test and Control Features3-wire Serial Interface Control SettingTable 11. 3-wire Serial Interface Control SettingsMode C

37 AT84AD001B 2153C–BDC–04/043-wire Serial Interface and Data DescriptionThe 3-wire bus is activated with the control bit mode set to 1. The length o

38AT84AD001B 2153C–BDC–04/04Notes: 1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and

39 AT84AD001B 2153C–BDC–04/04Table 13. 3-wire Serial Interface Data Setting Description Setting for Address: 000 D15 D14 D13 D12 D11 D10 D9(1)D8 D7

4AT84AD001B 2153C–BDC–04/04Typical ApplicationsFigure 2. Satellite Receiver ApplicationBandpassAmplifier11..12 GHz Local oscillatorBandpassAmplifier

40AT84AD001B 2153C–BDC–04/04Notes: 1. D9 must be set to “0”2. Mode standby channel I: use analog input I Vini, Vinib and Clocki.3. Mode standby chann

41 AT84AD001B 2153C–BDC–04/04• A minimum of one clock cycle with “sldn” returned at 1 is requested to close the write procedure and make the interfac

42AT84AD001B 2153C–BDC–04/04Calibration Description The AT84AD001B offers the possibility of reducing offset and gain matching between the two ADC co

43 AT84AD001B 2153C–BDC–04/04The calibration phase is necessary when using the AT84AD001B in interlace mode, where one analog input is sampled at bot

44AT84AD001B 2153C–BDC–04/04Example:Address = 110Data =One should then obtain 01010101 on Port B and 10101010 on Port A.When the dynamic mode is chos

45 AT84AD001B 2153C–BDC–04/04The VBE diode’s forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure

46AT84AD001B 2153C–BDC–04/04Figure 50. Simplified Data Ready Reset Buffer ModelFigure 51. Analog Input ModelVCCD/2100Ω VCCDGNDDDDRBDDRBN100Ω50Ω5

47 AT84AD001B 2153C–BDC–04/04Figure 52. Data Output Buffer ModelDefinitions of TermsVCCOGNDODOAIO, DOAI7 DOBIO, DOBI7DOAION, DOAI7NDOBION, DOBI7NTab

48AT84AD001B 2153C–BDC–04/04ORTOvervoltage Recovery TimeThe time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on th

49 AT84AD001B 2153C–BDC–04/04TRDR Data Ready Reset DelayThe delay between the falling edge of the Data Ready output asynchronous reset signal (DDRB)

5 AT84AD001B 2153C–BDC–04/04Figure 3. Dual Channel Digital Oscilloscope ApplicationNote: Absolute maximum ratings are limiting values (referenced to

50AT84AD001B 2153C–BDC–04/04Using the AT84AD001B Dual 8-bit 1 Gsps ADCDecoupling, Bypassing and Grounding of Power SuppliesThe following figures show

51 AT84AD001B 2153C–BDC–04/04Analog Input ImplementationThe analog inputs of the dual ADC have been designed with a double pad implementa-tion as ill

52AT84AD001B 2153C–BDC–04/04Figure 57. Termination Method for the ADC Analog Inputs in AC Coupling ModeClock Implementation The ADC features two dif

53 AT84AD001B 2153C–BDC–04/04Figure 59. Single-ended Termination Method for Clock I or Clock QOutput Termination in 1:1 RatioWhen using the integrat

54AT84AD001B 2153C–BDC–04/04Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)Note: If the outputs are to be use

55 AT84AD001B 2153C–BDC–04/04Figure 61. Dual ADC and ASIC/FPGA Load Block DiagramNote: The demultiplexers may be internal to the ASIC/FPGA system.Po

56AT84AD001B 2153C–BDC–04/04Thermal CharacteristicsSimplified Thermal Model for LQFP 144 20 x 20 x 1.4 mmThe following model has been extracted from

57 AT84AD001B 2153C–BDC–04/04Thermal Resistance from Junction to AmbientThe thermal resistance from the junction to ambient is 25.2° C/W typical.Note

58AT84AD001B 2153C–BDC–04/04Ordering InformationPart Number Package Temperature Range Screening CommentsAT84XAD001BTD LQFP 144 Ambient PrototypeProto

59 AT84AD001B 2153C–BDC–04/04Packaging InformationFigure 63. Type of PackageNote: Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm.DA1A2ACC0.2

6AT84AD001B 2153C–BDC–04/04Electrical Operating CharacteristicsUnless otherwise specified: •VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V•VINI - VINB or VIN

Printed on recycled paper.2153C–BDC–04/040MDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly co

7 AT84AD001B 2153C–BDC–04/04Supply current (2 input clocks, 1:2 DMUX mode) - Analog - Digital - OutputICCAICCDICCO150290180180350215mASupply current

8AT84AD001B 2153C–BDC–04/04Note: The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off.Note: Gain s

9 AT84AD001B 2153C–BDC–04/04Notes: 1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode