Rainbow-electronics DS3131 Instrukcja Użytkownika Strona 1

1 of 174 112002 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions

DS3131 10 of 174 Figure 2-1. Block Diagram RC2RD2TC2TD2JTDOPCLKPAD[31:0]PRSTPCBE[3:0]PPAR PFRAMEPIRDYPTRDYPSTOPPIDSELPDEVSELPREQPGNTPPERRPSERRR

DS3131 100 of 174 Figure 9-11. Transmit DMA Memory Organization Free Data Buffer SpaceTransmit Pending-Queue Descriptors: Contains Index Pointers

DS3131 101 of 174 Figure 9-12. Transmit DMA Packet Handling Buffer 1Packet 11st Descriptor(EOF=0/CV=0)Buffer 2Packet 12nd Descriptor(EOF=0/CV=0)Bu

DS3131 102 of 174 Figure 9-13. Transmit DMA Priority Packet Handling Buffer 1 Packet 1 1st Descriptor (EOF=0/CV=0) Buffer 2 Packet 1 2nd Descripto

DS3131 103 of 174 DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed trans

DS3131 104 of 174 descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second option allows the softwa

DS3131 105 of 174 9.3.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in m

DS3131 106 of 174 Figure 9-16. Transmit Packet Descriptors dword 0 Data Buffer Address (32) dword 1 EOF CV unused Byte Count (13) Next Descripto

DS3131 107 of 174 9.3.3 Pending Queue The host writes to the transmit pending queue the location of the readied descriptor, channel number, and contr

DS3131 108 of 174 The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descriptor

DS3131 109 of 174 Figure 9-18. Transmit Pending-Queue Structure Once the transmit DMA is activated (by setting the TDE contro

DS3131 11 of 174 Figure 2-2. Configuration Options 28Bit-SynchronousHDLC ControllersLocal BusPCI Bus28 SerialInterfaces(Ports 0 to 27)LBPXS28 Bit

DS3131 110 of 174 Register Name: TDMAQ Register Description: Transmit DMA Queues Control Register Address: 0880h Bit # 7 6 5 4 3 2 1 0 Name re

DS3131 111 of 174 9.3.4 Done Queue The DMA writes to the transmit done queue when it has finished either transmitting a complete packet chain or a co

DS3131 112 of 174 The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmission

DS3131 113 of 174 Figure 9-20. Transmit Done-Queue Structure Once the transmit DMA is activated (through the TDE control bit

DS3131 114 of 174 Done-Queue FIFO Flush Timer To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the transmit done-queu

DS3131 115 of 174 Register Name: TDMAQ Register Description: Transmit DMA Queues Control Register Address: 0880h Bit # 7 6 5 4 3 2 1 0 Name res

DS3131 116 of 174 9.3.5 DMA Configuration RAM The device contains an on-board set of 240 dwords (6 dwords per channel times 40 channels) that are us

DS3131 117 of 174 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit ad

DS3131 118 of 174 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmi

DS3131 119 of 174 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit val

DS3131 12 of 174 Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions

DS3131 120 of 174 Register Name: TDMAC Register Description: Transmit DMA Configuration Register Address: 0874h Bit # 7 6 5 4 3 2 1 0 Name D7 D

DS3131 121 of 174 10. PCI BUS 10.1 General Description of Operation The PCI block interfaces the DMA block to an external high-speed bus. The PCI

DS3131 122 of 174 10.1.1 PCI Read Cycle A read cycle on the PCI bus is shown in Figure 10-2. During clock cycle #1, the initiator asserts the PFRAME

DS3131 123 of 174 10.1.2 PCI Write Cycle A write cycle on the PCI bus is shown in Figure 10-3. During clock cycle #1, the initiator asserts the PFR

DS3131 124 of 174 10.1.3 PCI Bus Arbitration The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting PR

DS3131 125 of 174 10.1.5 PCI Target Retry Targets can terminate the requested bus transaction before any data is transferred because the target is b

DS3131 126 of 174 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt t

DS3131 127 of 174 10.1.8 PCI Fast Back-to-Back Fast back-to-back transactions are two consecutive bus transactions without the usually required idle

DS3131 128 of 174 10.2 PCI Configuration Register Description Register Name: PVID0 Register Description: PCI Vendor ID/Device ID Register 0 Reg

DS3131 129 of 174 10.2.1 Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it d

DS3131 13 of 174 Table 2-B. Initialization Steps INITIALIZATION STEP COMMENTS 1) System Reset System reset can be invoked by either hardware actio

DS3131 130 of 174 10.2.2 Status Bits (PCMD0) The upper words in the PCMD0 register are the status portion, which report events as they occur. As pr

DS3131 131 of 174 Register Name: PRCC0 Register Description: PCI Revision ID/Class Code Register 0 Register Address: 0x008h LSB Revision ID (Read

DS3131 132 of 174 Register Name: PDCM Register Description: PCI Device Configuration Memory Base Address Register Register Address: 0x010h LSB Ba

DS3131 133 of 174 Register Name: PVID1 Register Description: PCI Vendor ID/Device ID Register 1 Register Address: 0x100h LSB Vendor ID (Read Onl

DS3131 134 of 174 10.2.3 Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it d

DS3131 135 of 174 10.2.4 Status Bits (PCMD1) The upper words in the PCMD1 register are the status portion, which report events as they occur. As me

DS3131 136 of 174 Register Name: PRCC1 Register Description: PCI Revision ID/Class Code Register 1 Register Address: 0x108h LSB Revision ID (Rea

DS3131 137 of 174 Register Name: PLBM Register Description: PCI Local Bus Memory Base Address Register Register Address: 0x110h LSB Base Address

DS3131 138 of 174 11. LOCAL BUS 11.1 General Description The DS3131’s local bus can be either enabled or disabled. When it is disabled, the device u

DS3131 139 of 174 Figure 11-1. Bridge Mode Figure 11-2. Bridge Mode with Arbitration Enabled xDSLTransceiverLocal BusDS3131 BOSSHo

DS3131 14 of 174 3. SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS3131. Signal names foll

DS3131 140 of 174 Figure 11-3. Configuration Mode xDSL Transceiver Local BusDS3131 Host Processor and Main Memory PCI / CustomBusblb_cfgc CPU Conf

DS3131 141 of 174 11.1.1 PCI Bridge Mode In the PCI bridge mode, data from the PCI bus can be transferred to the local bus. The local bus acts as a “

DS3131 142 of 174 If the local bus is used as 16-bit bus, then the LBW control bit must be set to 0. In 16-bit accesses, the host can either perform

DS3131 143 of 174 Bridge Mode Interrupt In the PCI bridge mode, the local bus can detect an external interrupt through the LINT signal. If the local

DS3131 144 of 174 Figure 11-4. Local Bus Access Flowchart PCI Host Initiates aLocal Bus AccessIs Arbitration Enabledfor the Local Bus?Is the Loca

DS3131 145 of 174 11.2 Local Bus Bridge Mode Control Register Description Register Name: LBBMC Register Description: Local Bus Bridge Mode Contr

DS3131 146 of 174 Bit 6/Local Bus Width (LBW) 0 = 16 bits 1 = 8 bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four

DS3131 147 of 174 11.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitratio

DS3131 148 of 174 Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) A

DS3131 149 of 174 Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDYLRDYLRDY

DS3131 15 of 174 PIN NAME TYPE FUNCTION T18 TD3 O Transmit Serial Data for Port 3 T20 TD4 O Transmit Serial Data for Port 4 P17 TD5 O Trans

DS3131 150 of 174 Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction T

DS3131 151 of 174 Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110)

DS3131 152 of 174 Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110

DS3131 153 of 174 Figure 11-11. 16-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDYLRD

DS3131 154 of 174 Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDYLRD

DS3131 155 of 174 12. JTAG 12.1 JTAG Description The DS3131 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional pu

DS3131 156 of 174 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure 1

DS3131 157 of 174 Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS3131 power-up. The instruction register contains the I

DS3131 158 of 174 Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stag

DS3131 159 of 174 12.3 Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output

DS3131 16 of 174 PIN NAME TYPE FUNCTION Y5 PAD26 I/O PCI Multiplexed Address and Data Bit 26 W5 PAD27 I/O PCI Multiplexed Address and Data Bit

DS3131 160 of 174 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register. An op

DS3131 161 of 174 13. AC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage on Any Lead with Respect to VSS (except VDD) -0.3V to 5.5VSupply Voltage

DS3131 162 of 174 AC CHARACTERISTICS: LAYER 1 PORTS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RC/TC Clo

DS3131 163 of 174 AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TY

DS3131 164 of 174 AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS

DS3131 165 of 174 Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams t9Address ValidData Valid

DS3131 166 of 174 Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) Address V

DS3131 167 of 174 AC CHARACTERISTICS: PCI BUS INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PCLK

DS3131 168 of 174 AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNI

DS3131 169 of 174 14. MECHANICAL DIMENSIONS 14.1 272 PBGA Package

DS3131 17 of 174 PIN NAME TYPE FUNCTION C1 RC25 I Receive Serial Clock for Port 25 D3 RC26 I Receive Serial Clock for Port 26 C2 RC27 I Rec

DS3131 170 of 174 15. APPLICATIONS This section describes some possible applications for the DS3131. There are many potential configurations but only

DS3131 171 of 174 Figure 15-2 shows an application where up to 40 T1 or E1 ports are interfaced to a single DS3131. In this application, the quad T1

DS3131 172 of 174 Figure 15-3 shows an application where three T3 or E3 framers are interfaced to a single DS3131. The DS3131 is used to terminate b

DS3131 173 of 174 15.2 DSL and Cable Modem Applications Figure 15-4 shows an application where multiple xDSL or cable modems are interfaced to a sin

DS3131 174 of 174 15.3 ONET/SDH Applications Figure 15-5 shows an application where the overhead links on multiple SONET or SDH lines are being termi

DS3131 18 of 174 PIN NAME TYPE FUNCTION B3 LA16–RD29 I/O–I Local Bus Address Bit 16–Receive Serial Data for Port 29 B2 LA17–RC29 I/O–I Local B

DS3131 19 of 174 Figure 3-1. Signal Floorplan 1234567891011121314151617181920Y RC0 PCLK PAD30 PAD29 PAD26 PIDSEL PAD21 PAD18 PCBE2* PTRDY*PDEV-SEL*P

DS3131 2 of 174 TABLE OF CONTENTS 1. MAIN FEATURES ...

DS3131 20 of 174 3.2 Serial Port Interface Signal Description Signal Name: RC0 to RC39 Signal Description: Receive Serial Clock Signal Type:

DS3131 21 of 174 Signal Name: LBPXS Signal Description: Local Bus or Port Extension Select Signal Type: Input (with internal 10kΩ pullup) This

DS3131 22 of 174 Signal Name: LRDLRDLRDLRD (LDSLDSLDSLDS) Signal Description: Local Bus Read Enable (Local Bus Data Strobe) Signal Type: Input

DS3131 23 of 174 Signal Name: LBHELBHELBHELBHE Signal Description: Local Bus Byte-High Enable (PCI Bridge Mode Only) Signal Type: Output (thre

DS3131 24 of 174 3.5 PCI Bus Signal Description Signal Name: PCLK Signal Description: PCI and System Clock Signal Type: Input (Schmitt trigg

DS3131 25 of 174 updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK.

DS3131 26 of 174 Signal Name: PREQPREQPREQPREQ Signal Description: PCI Bus Request Signal Type: Output (three-state capable) The initiator ass

DS3131 27 of 174 Signal Name: PXBLASTPXBLASTPXBLASTPXBLAST Signal Description: PCI Extension Burst Last Signal Type: Output This active-low si

DS3131 28 of 174 4. MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device configu

DS3131 29 of 174 4.3 Receive Port Registers (1xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0100 RP0CR Receive Port 0 Control Register 6.2 0104 RP1

DS3131 3 of 174 9.2.4 Done Queue...

DS3131 30 of 174 4.4 Transmit Port Registers (2xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0200 TP0CR Transmit Port 0 Control Register 6.2 0204 TP

DS3131 31 of 174 4.5 Receive HDLC Control Registers (3xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0300 RH0CR Receive Port 0 HDLC Control Register 7

DS3131 32 of 174 4.6 TRANSMIT HDLC CONTROL REGISTERS (4xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0400 TH0CR Transmit Port 0 HDLC Control Register

DS3131 33 of 174 4.7 BERT Registers (5xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0500 BERTC0 BERT Control 0 6.4 0504 BERTC1 BERT Control 1 6.4

DS3131 34 of 174 4.9 Transmit DMA Registers (8xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0800 TPQBA0 Transmit Pending-Queue Base Address 0 (lower w

DS3131 35 of 174 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS NAME REGISTER SECTION 0x000/0A00 PVID0 PCI Vendor ID

DS3131 36 of 174 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID)

DS3131 37 of 174 5.2 Master Configuration Register Description The master configuration (MC) register is used by the host to enable the receive and

DS3131 38 of 174 Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either Little Endian or Big E

DS3131 39 of 174 5.3 Status and Interrupt 5.3.1 General Description of Operation There are two status registers in the device, status master (SM) an

DS3131 4 of 174 LIST OF FIGURES Figure 2-1. Block Diagram ...

DS3131 40 of 174 Figure 5-1. Status Register Block Diagram for SM ORSBERTPSERRPPERRn/an/aLBINT LBEBERTEC0 Bit 1 (BECO)BERTEC0 Bit 2 (BBCO)BERTC0 Bi

DS3131 41 of 174 5.3.2 Status and Interrupt Register Description Register Name: SM Register Description: Status Master Register Register Address

DS3131 42 of 174 Register Name: ISM Register Description: Interrupt Mask Register for SM Register Address: 0024h Bit # 7 6 5 4 3 2 1 0 Name res

DS3131 43 of 174 Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive HDLC channels detects an

DS3131 44 of 174 for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LI

DS3131 45 of 174 Register Name: ISDMA Register Description: Interrupt Mask Register for SDMA Register Address: 002Ch Bit # 7 6 5 4 3 2 1 0 Name

DS3131 46 of 174 Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit for

DS3131 47 of 174 6. LAYER 1 6.1 General Description Each port on the DS3131 contains a dedicated bit-synchronous HDLC controller for that port. The

DS3131 48 of 174 Figure 6-1. Layer 1 Port Interface Block Diagram

DS3131 49 of 174 6.2 Port Register Descriptions Receive Side Control Bits (one each for all 40 ports) Register Name: RP[n]CR, where n = 0 to 39

DS3131 5 of 174 Figure 11-9. 8-Bit Read Cycle ...

DS3131 50 of 174 Transmit Side Control Bits (one each for all 40 ports) Register Name: TP[n]CR, where n = 0 to 39 for each port Register Descripti

DS3131 51 of 174 6.3 BERT The BERT block is capable of generating and detecting the following patterns:  The pseudorandom patterns 2E7, 2E11, 2E1

DS3131 52 of 174 6.4 BERT Register Description Figure 6-3. BERT Register Set BERTC0: BERT Control 0 LSBreserved TINV RINV PS2 PS1 PS0 LC RESYNC

DS3131 53 of 174 Register Name: BERTC0 Register Description: BERT Control Register 0 Register Address: 0500h Bit # 7 6 5 4 3 2 1 0 Name reserv

DS3131 54 of 174 Repetitive Pattern Length Map Length Code Length Code Length Code Length Code 17 Bits 0000 18 Bits 0001 19 Bits 0010 20 B

DS3131 55 of 174 Register Name: BERTC1 Register Description: BERT Control Register 1 Register Address: 0504h Bit # 7 6 5 4 3 2 1 0 Name

DS3131 56 of 174 Register Name: BERTBRP0 Register Description: BERT Repetitive Pattern Set 0 Register Address: 0508h Register Name: BERTBRP1 R

DS3131 57 of 174 Register Name: BERTBC0 Register Description: BERT 32-Bit Bit Counter (lower word) Register Address: 0510h Register Name: BERT

DS3131 58 of 174 Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when

DS3131 59 of 174 7. HDLC 7.1 General Description Each port on the DS3131 has a dedicated bit-synchronous HDLC controller that can operate up to 52

DS3131 6 of 174 1. MAIN FEATURES  Layer 1 40 independent bit-synchronous physical ports capable of speeds up to 52Mbps Each port can be independen

DS3131 60 of 174 Table 7-B. Receive Bit-Synchronous HDLC Packet Processing Outcomes OUTCOME CRITERIA EOF/Normal Packet Integral number of packets &

DS3131 61 of 174 Table 7-D. Transmit Bit-Synchronous HDLC Functions Zero Stuffing Only used between opening and closing flags. Is disabled in betwee

DS3131 62 of 174 Bit 1/Receive Maximum Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC controller does not check to see if t

DS3131 63 of 174 Register Name: RHPL Register Description: Receive HDLC Maximum Packet Length Register Address: 03A0h Bit # 7 6 5 4 3 2 1 0 Name

DS3131 64 of 174 Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted after being generated.

DS3131 65 of 174 8. FIFO 8.1 General Description and Example The BoSS contains one 8kB FIFO for the receive path and another 8kB FIFO for the tran

DS3131 66 of 174 block pointer. The block pointer RAM tells the device how to link the eight blocks together to form a circular chain. The host must

DS3131 67 of 174 8.1.1 Receive High Watermark The high watermark tells the device how many blocks should be written into the receive FIFO by the HDLC

DS3131 68 of 174 8.2 FIFO Register Description Register Name: RFSBPIS Register Description: Receive FIFO Starting Block Pointer Indirect Select

DS3131 69 of 174 Register Name: RFBPIS Register Description: Receive FIFO Block Pointer Indirect Select Register Address: 0910h Bit # 7 6 5 4 3

DS3131 7 of 174 Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS3131’s ports are numbered 0 t

DS3131 70 of 174 Register Name: RFHWMIS Register Description: Receive FIFO High-Watermark Indirect Select Register Address: 0920h Bit # 7 6 5 4

DS3131 71 of 174 Register Name: TFSBPIS Register Description: Transmit FIFO Starting Block Pointer Indirect Select Register Address: 0980h Bit

DS3131 72 of 174 Register Name: TFBPIS Register Description: Transmit FIFO Block Pointer Indirect Select Register Address: 0990h Bit # 7 6 5 4

DS3131 73 of 174 Register Name: TFLWMIS Register Description: Transmit FIFO Low-Watermark Indirect Select Register Address: 09A0h Bit # 7 6 5 4

DS3131 74 of 174 9. DMA 9.1 Introduction The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vic

DS3131 75 of 174 Table 9-A. DMA Registers to be Configured by the Host on Power-Up ADDRESS NAME REGISTER SECTION 0700 RFQBA0 Receive Free-Queue

DS3131 76 of 174 9.2 Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host ke

DS3131 77 of 174 On an HDLC channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers fo

DS3131 78 of 174 Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space ava

DS3131 79 of 174 Figure 9-2. Receive DMA Memory Organization Free Data Buffer SpaceReceive Free-Queue Descriptors:Contains 32-Bit Addresses for Fre

DS3131 8 of 174 The FIFO transfers data from the HDLC engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable high

DS3131 80 of 174 9.2.2 Packet Descriptors A contiguous section up to 65,536 quad dwords that make up the receive packet descriptors resides in main m

DS3131 81 of 174 Figure 9-4. Receive Packet Descriptors dword 0 Data Buffer Address (32) dword 1 BUFS (3) Byte Count (13) Next Descriptor Pointer

DS3131 82 of 174 9.2.3 Free Queue The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors t

DS3131 83 of 174 Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty Stat

DS3131 84 of 174 Figure 9-6. Receive Free-Queue Structure Once the receive DMA is activated (by setting the

DS3131 85 of 174 Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (R

DS3131 86 of 174 Register Name: RDMAQ Register Description: Receive DMA Queues Control Register Address: 0780h Bit # 7 6 5 4 3 2 1 0 Name res

DS3131 87 of 174 9.2.4 Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the

DS3131 88 of 174 The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. T

DS3131 89 of 174 Figure 9-8. Receive Done-Queue Structure Once the receive DMA is activated (through the RDE control bit in th

DS3131 9 of 174 The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data ready to

DS3131 90 of 174 Buffer Write Threshold Setting In the DMA configuration RAM (Section 9.2.5), there is a host-controlled field called “threshold” (bi

DS3131 91 of 174 Register Name: RDQFFT Register Description: Receive Done-Queue FIFO Flush Timer Register Address: 0744h Bit # 7 6 5 4 3 2 1 0

DS3131 92 of 174 Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is flushed by sending all data

DS3131 93 of 174 9.2.5 DMA Configuration RAM There is a set of 120 dwords (3 dwords per channel times 40 channels) on-board the device that the host

DS3131 94 of 174 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of

DS3131 95 of 174 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 2; Bits 10 to 14/DMA Reserved. Could be any value when read. Should be set

DS3131 96 of 174 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive DMA configuration RAM, this bi

DS3131 97 of 174 9.3 Transmit Side 9.3.1 Overview The transmit DMA uses a scatter-gather technique to read packet data from main memory. The host ke

DS3131 98 of 174 Host Linking of Packets (Packet Chaining) The host also has the option to link multiple packets together in a chain. Through the ch

DS3131 99 of 174 Figure 9-10. Transmit DMA Operation 00h08hDone-Queue Descriptors(circular queue)04hFree Desc. Ptr.CH#5StatusFree Desc. Ptr.CH#1Sta