Rainbow-electronics DS14287 Instrukcja Użytkownika Pobierz pdf (Strona 15)

DS14285/DS14287

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PERIODIC INTERRUPT RATE AND

SQUARE WAVE OUTPUT FREQUENCY Table 2

SELECT BITS REGISTER A

RS3 RS2 RS1 RS0

PERIODIC

INTERRUPT RATE

SQW OUTPUT

FREQUENCY

0 0 0 0 None None

0 0 0 1 3.90625 ms 256 Hz

0 0 1 0 7.8125 ms 128 Hz

0011

122.070 µs

8.192 kHz

0100

244.141 µs

4.096 kHz

0101

488.281 µs

2.048 kHz

0110

976.5625 µs

1.024 kHz

0 1 1 1 1.953125 ms 512 Hz

1 0 0 0 3.90625 ms 256 Hz

1 0 0 1 7.8125 ms 128 Hz

1 0 1 0 15.625 ms 64 Hz

1 0 1 1 31.25 ms 32 Hz

1 1 0 0 62.5 ms 16 Hz

1 1 0 1 125 ms 8 Hz

1 1 1 0 250 ms 4 Hz

1 1 1 1 500 ms 2 Hz

UPDATE CYCLE

The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.

When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and

alarm bytes is frozen and will not update as the time increments. However, the time countdown chain

continues to update the internal copy of the buffer. This feature allows time to maintain accuracy

independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and

calendar information is consistent. The update cycle also compares each alarm byte with the

corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three

positions.

There are three methods that can handle access of the real-time clock that avoid any possibility of

accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If

enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read

valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared

before leaving the interrupt routine.

A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in

progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs

244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will

be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed

to read valid time/calendar data to exceed 244 µs.

The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in

that occur at a rate of greater than t

BUC

allow valid time and date information to be reached at each

occurrence of the periodic interrupt. The reads should be complete within 1 (t

PI/

+ t

BUC

) to ensure that

data is not read during the update cycle.

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