DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
_____________________________________________________________________ 5
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13: C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 14: Guaranteed by design.
Typical Operating Characteristics
(V
CC
= 5.0V, T
A
= +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
Komentarze do niniejszej Instrukcji