Rainbow-electronics AT89LP214 Instrukcja Użytkownika Pobierz pdf (Strona 75)

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

23.8.6 Timing Parameters

The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10

are shown in Table 23-6.

Table 23-6. Programming Interface Timing Parameters

Note: 1. t

SCK

is independent of t

CLCL

Symbol Parameter Min Max Units

CLCL

System Clock Cycle Time 0 60 ns

PWRUP

Power On to SS High Time 10 µs

POR

Power-on Reset Time 100 µs

PWRDN

SS Tristate to Power Off 1 µs

RLZ

RST Low to I/O Tristate t

CLCL

2 t

CLCL

STL

RST Low Settling Time 100 ns

RHZ

RST High to SS Tristate 0 2 t

CLCL

SCK

Serial Clock Cycle Time 200

(1)

SHSL

Clock High Time 75 ns

SLSH

Clock Low Time 50 ns

Rise Time 25 ns

Fall Time 25 ns

SIS

Serial Input Setup Time 10 ns

SIH

Serial Input Hold Time 10 ns

SOH

Serial Output Hold Time 10 ns

SOV

Serial Output Valid Time 35 ns

SOE

Output Enable Time 10 ns

SOX

Output Disable Time 25 ns

SSE

SS Enable Lead Time t

SLSH

SSD

SS Disable Lag Time t

SLSH

ZSS

SCK Setup to SS Low 25 ns

SSZ

SCK Hold after SS High 25 ns

Write Cycle Time 2.5 ms

AWR

Write Cycle with Auto-Erase Time 5 ms

ERS

Chip Erase Cycle Time 7.5 ms

1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 89 90

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