Rainbow-electronics ATtiny43U Instrukcja Użytkownika Pobierz pdf (Strona 90)

8048B–AVR–03/09

ATtiny43U

Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O

/8)

12.9 Register Description

12.9.1 TCCR0A – Timer/Counter Control Register A

12.9.2 TCCR1A – Timer/Counter Control Register A

• Bits 7:6 – COMnA[1:0]: Compare Match Output A Mode

These bits control the Output Compare pin (OCnA) behavior. If one or both of the COMnA[1:0]

bits are set, the OCnA output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA pin

must be set in order to enable the output driver.

When OCnA is connected to the pin, the function of the COMnA[1:0] bits depends on the

WGMn[2:0] bit setting. Table 12-2 on page 90 shows the COMnA[1:0] bit functionality when the

WGMn[2:0] bits are set to a normal or CTC mode (non-PWM).

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

Bit 7 6 5 4 3 2 1 0

0x30 (0x50)

COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

0x2F (0x4F)

COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 12-2. Compare Output Mode, non-PWM Mode

COMnA1 COMnA0 Description

0 0 Normal port operation, OCnA disconnected.

0 1 Toggle OCnA on Compare Match

1 0 Clear OCnA on Compare Match

1 1 Set OCnA on Compare Match

1 2 ... 85 86 87 88 89 90 91 92 93 94 95 ... 181 182

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