Rainbow-electronics ATmega161L Instrukcja Użytkownika Strona 1

1Features• High-performance, Low-power AVR®8-bit Microcontroller• Advanced RISC Architecture– 130 Powerful Instructions – Most Single Clock Cycle Exec

10ATmega161(L)1228C–AVR–08/02The General PurposeRegister FileFigure 6 shows the structure of the 32 general purpose working registers in the CPU.Figur

100ATmega161(L)1228C–AVR–08/02Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.Three I/O address locations are alloca

101ATmega161(L)1228C–AVR–08/02has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pinsare tri-stated when a reset co

102ATmega161(L)1228C–AVR–08/02Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the fi

103ATmega161(L)1228C–AVR–08/02Figure 66. Port D Schematic Diagram (Pins PD2 and PD3)Figure 67. Port D Schematic Diagram (Pin PD4)WP:WD:RL:RP:RD:n:m:WR

104ATmega161(L)1228C–AVR–08/02Figure 68. Port D Schematic Diagram (Pin PD5)Figure 69. Port D Schematic Diagram (Pin PD6)COMP. MATCH 1AFOC1APWM10PWM11W

105ATmega161(L)1228C–AVR–08/02Figure 70. Port D Schematic Diagram (Pin PD7)WP:WD:RL:RP:RD:RE:SRE:WRITE PORTDWRITE DDRDREAD PORTD LATCHREAD PORTD PINRE

106ATmega161(L)1228C–AVR–08/02Port E Port E is a 3-bit bi-directional I/O port with internal pull-up resistors.Three I/O address locations are allocat

107ATmega161(L)1228C–AVR–08/02Note: 1. n: 2,1,0, pin number.Alternate Functions of Port E The alternate pin configuration is as follows:• OC1B– Port E

108ATmega161(L)1228C–AVR–08/02Port E Schematics Figure 71. Port E Schematic Diagram (Pin PE0)Figure 72. Port E Schematic Diagram (Pin PE1)DATA BUSDDQQ

109ATmega161(L)1228C–AVR–08/02Figure 73. Port E Schematic Diagram (Pin PE2)PE2DDE2PORTE2COMP. MATCH 1BCOM1B0COM1B1WP:WD:RL:RP:RD:WRITE PORTEWRITE DDRE

11ATmega161(L)1228C–AVR–08/02In the different Addressing modes, these address registers have functions as fixed dis-placement, automatic increment and

110ATmega161(L)1228C–AVR–08/02MemoryProgrammingBoot Loader Support The ATmega161 provides a mechanism for downloading and uploading program codeby the

111ATmega161(L)1228C–AVR–08/02• Protect the entire Flash from a software update by the Boot Loader program• Only protect the Boot Loader section from

112ATmega161(L)1228C–AVR–08/02Note: 1. “1” means unprogrammed, “0” means programmedCapabilities of the BootLoaderThe program code within the Boot Load

113ATmega161(L)1228C–AVR–08/02Fill the Temporary Buffer To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write“000

114ATmega161(L)1228C–AVR–08/02Store Program MemoryControl Register – SPMCRThe Store Program Memory Control Register contains the control bits needed t

115ATmega161(L)1228C–AVR–08/02EEPROM Write PreventsWritingtoSPMCRNote that an EEPROM write operation will block all software programming to Flash.Read

116ATmega161(L)1228C–AVR–08/02Program MemoryLock bitsThe ATmega161 MCU provides six Lock bits that can be left unprogrammed (“1”)orcanbe programmed (“

117ATmega161(L)1228C–AVR–08/02• CKSEL2..0: See Table 4, “Reset Delay Selections(3),” on page 26, for whichcombination of CKSEL2..0 to use. Default val

118ATmega161(L)1228C–AVR–08/02Parallel Programming This section describes how to parallel program and verify Flash Program memory,EEPROM Data memory,

119ATmega161(L)1228C–AVR–08/02Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply 4.5 - 5.5V between

12ATmega161(L)1228C–AVR–08/02SRAM Data Memory Figure 8 shows how the ATmega161 SRAM memory is organized.Figure 8. SRAM OrganizationThe lower 1120 Data

120ATmega161(L)1228C–AVR–08/02Programming the Flash The Flash is organized as 128 pages of 128 bytes each. When programming the Flash,the program data

121ATmega161(L)1228C–AVR–08/021. Give WR a negative pulse. This starts programming of the entire page of data.RDY/BSYgoes low.2. Wait until RDY/BSYgoe

122ATmega161(L)1228C–AVR–08/02Programming the EEPROM The programming algorithm for the EEPROM Data memory is as follows (refer to “Pro-gramming the Fl

123ATmega161(L)1228C–AVR–08/02Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming theFlash” on page 120

124ATmega161(L)1228C–AVR–08/02Reading the Fuse and LockBitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to “Programmingthe Fl

125ATmega161(L)1228C–AVR–08/02Notes: 1. tWLRHis valid for the Write EEPROM, Write Fuse bits and Write Lock bits commands.2. tWLRH_CEis valid for the C

126ATmega161(L)1228C–AVR–08/02Serial ProgrammingAlgorithmWhen writing serial data to the ATmega161, data is clocked on the rising edge of SCK.When rea

127ATmega161(L)1228C–AVR–08/02tWD_FLASHbefore programming the next page. As a chip-erased device contains $FF inall locations, programming of addresse

128ATmega161(L)1228C–AVR–08/02.Note: 1. a = address high bitsb = address low bitsH =0– Low byte, 1 – High Byteo = data outi =datainx = don’tcare1=lock

129ATmega161(L)1228C–AVR–08/02Serial ProgrammingCharacteristicsFigure 81. Serial Programming TimingTable 49. Serial Programming Characteristics, TA=-4

13ATmega161(L)1228C–AVR–08/02The five different Addressing modes for the Data memory cover: Direct, Indirect withDisplacement, Indirect, Indirect with

130ATmega161(L)1228C–AVR–08/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°Cto+125°C

131ATmega161(L)1228C–AVR–08/02Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value wh

132ATmega161(L)1228C–AVR–08/02If IOHexceeds the test condition, VOHmay exceed the related specification. Pins are not guaranteed to source currentgrea

133ATmega161(L)1228C–AVR–08/02External Data Memory TimingNotes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the

134ATmega161(L)1228C–AVR–08/02Table 53. External Data Memory Characteristics, 4.0 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0Symbol Parameter8 MHz Oscillator Va

135ATmega161(L)1228C–AVR–08/02Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2. T

136ATmega161(L)1228C–AVR–08/02Figure 83. External Memory Timing (SRWn1 = 0, SRWn0 = 0)Figure 84. External Memory Timing (SRWn1 = 0, SRWn0 = 1)ALEWRRDA

137ATmega161(L)1228C–AVR–08/02Figure 85. External Memory Timing (SRWn1 = 1, SRWn0 = 0)Figure 86. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)Note:

138ATmega161(L)1228C–AVR–08/02TypicalCharacteristicsAnalog Comparator offset voltage is measured as absolute offset.Figure 87. Analog Comparator Offse

139ATmega161(L)1228C–AVR–08/02Figure 89. Analog Comparator Input Leakage CurrentFigure 90. Watchdog Oscillator Frequency vs. VCCSink and source capabi

14ATmega161(L)1228C–AVR–08/02Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d(Rd).I/O Direct Figure 11. I/O D

140ATmega161(L)1228C–AVR–08/02Figure 91. Pull-up Resistor Current vs. Input VoltageFigure 92. Pull-up Resistor Current vs. Input Voltage02040608010012

141ATmega161(L)1228C–AVR–08/02Figure 93. I/O Pin Sink Current vs. Output VoltageFigure 94. I/O Pin Source Current vs. Output Voltage0102030405060700 0

142ATmega161(L)1228C–AVR–08/02Figure 95. I/O Pin Sink Current vs. Output VoltageFigure 96. I/O Pin Source Current vs. Output Voltage05101520250 0.5 1

143ATmega161(L)1228C–AVR–08/02Figure 97. I/O Pin Input Threshold vs. VCCFigure 98. I/O Pin Input Hysteresis vs. VCC00.511.522.52.7 4.0 5.0THRESHOLD VO

144ATmega161(L)1228C–AVR–08/02Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C page 21$

145ATmega161(L)1228C–AVR–08/02Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memor

146ATmega161(L)1228C–AVR–08/02Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr

147ATmega161(L)1228C–AVR–08/02BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None 1/2BRTC k Branch if T-flag Cleared if (T = 0) then PC ←

148ATmega161(L)1228C–AVR–08/02SEZ Set Zero Flag Z ← 1Z1CLZ Clear Zero Flag Z ← 0Z1SEI Global Interrupt Enable I ← 1I1CLI Global Interrupt Disable I ←

149ATmega161(L)1228C–AVR–08/02Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering

15ATmega161(L)1228C–AVR–08/02Data Indirect withDisplacementFigure 13. Data Indirect with DisplacementOperand address is the result of the Y- or Z-regi

150ATmega161(L)1228C–AVR–08/02Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0

151ATmega161(L)1228C–AVR–08/0240P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1

152ATmega161(L)1228C–AVR–08/02ErrataATmega161 Rev. E • PWM not Phase Correct• Increased Interrupt Latency• Interrupt Return Fails when Stack Pointer A

153ATmega161(L)1228C–AVR–08/021. Store Program Memory Instruction May FailAt certain frequencies and voltages, the store program memory (SPM) instruct

154ATmega161(L)1228C–AVR–08/02Data Sheet ChangeLog for ATmega161This document contains a log on the changes made to the data sheet for ATmega161.Chang

iATmega161(L)1228C–AVR–08/02Table of ContentsFeatures...

iiATmega161(L)1228C–AVR–08/02Internal Voltage Reference ... 83Voltage Reference Enable Si

iiiATmega161(L)1228C–AVR–08/0240P6 ... 1

ivATmega161(L)1228C–AVR–08/02

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

16ATmega161(L)1228C–AVR–08/02Data Indirect with Post-incrementFigure 16. Data Indirect Addressing with Post-incrementThe X-, Y-, or Z-register is incr

17ATmega161(L)1228C–AVR–08/02Program execution continues at address contained by the Z-register (i.e., the PC isloaded with the contents of the Z-regi

18ATmega161(L)1228C–AVR–08/02Figure 21. The Parallel Instruction Fetches and Instruction ExecutionsFigure 22 shows the internal timing concept for the

19ATmega161(L)1228C–AVR–08/02l/O Memory The I/O space definition of the ATmega161 is shown in Table 1.Table 1. ATmega161 I/O Space(1)I/O Address(SRAM

2ATmega161(L)1228C–AVR–08/02Pin Configuration12345678910111213141516171819204039383736353433323130292827262524232221(OC0/T0) PB0(OC2/T1) PB1(RXD1/AIN0

20ATmega161(L)1228C–AVR–08/02Note: 1. Reserved and unused locations are not shown in this table.$1C ($3C) EECR EEPROM Control Register$1B($3B) PORTA D

21ATmega161(L)1228C–AVR–08/02All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations areaccessed by the IN and OUT instructi

22ATmega161(L)1228C–AVR–08/02• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result after the different arithmetic and logicoperati

23ATmega161(L)1228C–AVR–08/02Note: 1. If BOOTRST fuse is programmed, the Reset Vector is located on program address$1e00, see Table 39 on page 112 for

24ATmega161(L)1228C–AVR–08/02$01a jmp UART_RXC0 ; UART0 RX Complete Handler$01c jmp UART_RXC1 ; UART1 RX Complete Handler$01e jmp UART_DRE0 ; UDR0 Emp

25ATmega161(L)1228C–AVR–08/02Reset Sources The ATmega161 has three sources of Reset:• Power-on Reset. The MCU is reset when the supply voltage is belo

26ATmega161(L)1228C–AVR–08/02Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).‘Notes: 1. The CKSEL fus

27ATmega161(L)1228C–AVR–08/02Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is nominal

28ATmega161(L)1228C–AVR–08/02External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longerthan 500 ns will genera

29ATmega161(L)1228C–AVR–08/02MCU Status Register –MCUSRThe MCU Status Register provides information on which reset source caused an MCUReset.• Bits 7.

3ATmega161(L)1228C–AVR–08/02Description The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerf

30ATmega161(L)1228C–AVR–08/02Note that the Status Register is not automatically stored when entering an interrupt rou-tine or restored when returning

31ATmega161(L)1228C–AVR–08/02• Bits 4..0 – Res: Reserved BitsThese bits are reserved bits in the ATmega161 and always read as zero.General Interrupt F

32ATmega161(L)1228C–AVR–08/02• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in

33ATmega161(L)1228C–AVR–08/02Timer/Counter Interrupt FlagRegister – TIFR• Bit 7– TOV1: Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overf

34ATmega161(L)1228C–AVR–08/02Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2Compare match Interrupt is executed.• Bit

35ATmega161(L)1228C–AVR–08/02grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before theexecution of the SLEEP instruction.•

36ATmega161(L)1228C–AVR–08/02Extended MCU ControlRegister – EMCUCRThe Extended MCU Control Register contains control bits for External Interrupt 2, Sl

37ATmega161(L)1228C–AVR–08/02Analog Comparator interrupt is not required, the Analog Comparator can be powereddown by setting the ACD bit in the Analo

38ATmega161(L)1228C–AVR–08/02Timer/Counters The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs andone 16-bit T/C. Timer/Coun

39ATmega161(L)1228C–AVR–08/02Figure 30. Timer/Counter2 PrescalerThe clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default con-ne

4ATmega161(L)1228C–AVR–08/02Block Diagram Figure 1. The ATmega161 Block DiagramPROGRAMMINGLOGICSPIUARTSPB0 - PB7VCCGND+-ANALOGCOMPARATOR8-BIT DATA BUS

40ATmega161(L)1228C–AVR–08/02• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0When this bit is set (one), the Timer/Counter1 and Time

41ATmega161(L)1228C–AVR–08/02Figure 32. Timer/Counter2 Block DiagramThe 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an exter

42ATmega161(L)1228C–AVR–08/02Timer/Counter0 ControlRegister – TCCR0Timer/Counter2 ControlRegister – TCCR2• Bit 7– FOC0/FOC2: Force Output CompareWriti

43ATmega161(L)1228C–AVR–08/02prescaling of 1 is used, and the compare register is set to C, the timer will count as fol-lows if CTC0/CTC2 is set:...|C

44ATmega161(L)1228C–AVR–08/02Timer Counter0 – TCNT0Timer/Counter2 – TCNT2These 8-bit registers contain the value of the Timer/Counters.Both Timer/Coun

45ATmega161(L)1228C–AVR–08/02PWM Modes (Up/Down andOverflow)The two different PWM modes are selected by the CTC0 or CTC2 bit in theTimer/Counter Contr

46ATmega161(L)1228C–AVR–08/02Figure 33. Effects of Unsynchronized OCR Latching in Up/Down ModeFigure 34. Effects of Unsynchronized OCR Latching in Ove

47ATmega161(L)1228C–AVR–08/02In up/down PWM mode, the Timer Overflow Flag (TOV0 or TOV2) is set when thecounter advances from $00. In overflow PWM mod

48ATmega161(L)1228C–AVR–08/02Asynchronous Operation ofTimer/Counter2When Timer/Counter2 operates asynchronously, some considerations must be taken:• W

49ATmega161(L)1228C–AVR–08/02• Description of wake-up from Power-save mode when the timer is clockedasynchronously: When the interrupt condition is me

5ATmega161(L)1228C–AVR–08/02Pin DescriptionsVCC Supply voltage.GND Ground.Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can

50ATmega161(L)1228C–AVR–08/02clock period. The external clock signal is sampled on the rising edge of the internal CPUclock.The 16-bit Timer/Counter1

51ATmega161(L)1228C–AVR–08/02• Bits 5, 4 – COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0The COM1B1 and COM1B0 control bits determine any output

52ATmega161(L)1228C–AVR–08/02• Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select BitsThese bits select PWM operation of Timer/Counter1 as specifi

53ATmega161(L)1228C–AVR–08/02• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0The Clock Select1 bits 2, 1 and 0 define the prescaling

54ATmega161(L)1228C–AVR–08/02The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with readand write access. If Timer/Counter1 is

55ATmega161(L)1228C–AVR–08/02The Input Capture Register is a 16-bit read-only register.When the rising or falling edge (according to the Input Capture

56ATmega161(L)1228C–AVR–08/02Note: 1. X = A or BNote that in the PWM mode, the 8, 9 or 10 least significant OCR1A/OCR1B bits(depends of resolution), w

57ATmega161(L)1228C–AVR–08/02Figure 38. Effects of Unsynchronized OCR1 Latching in Overflow Mode1Note: 1. Note: X = A or BDuring the time between the

58ATmega161(L)1228C–AVR–08/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.This is the typical va

59ATmega161(L)1228C–AVR–08/02WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-dure must be followed:1. In the same op

6ATmega161(L)1228C–AVR–08/02Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that canbe configured for

60ATmega161(L)1228C–AVR–08/02EEPROM Read/WriteAccessThe EEPROM Access Registers are accessible in the I/O space.The write access time is in the range

61ATmega161(L)1228C–AVR–08/02EEPROM Control Register –EECR• Bits 7..4– Res: Reserved BitsThese bits are reserved bits in the ATmega161 and will always

62ATmega161(L)1228C–AVR–08/02bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-tion is executed.The user should p

63ATmega161(L)1228C–AVR–08/02Serial PeripheralInterface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween

64ATmega161(L)1228C–AVR–08/02The interconnection between Master and Slave CPUs with SPI is shown in Figure 41.The PB7(SCK) pin is the Clock Output in

65ATmega161(L)1228C–AVR–08/02SS Pin Functionality When the SPI is configured as a Master (MSTR in SPCR is set), the user can determinethe direction of

66ATmega161(L)1228C–AVR–08/02Figure 43. SPI Transfer Format with CPHA = 1 and DORD = 0SPIControlRegister– SPCR• Bit 7– SPIE: SPI Interrupt EnableThis

67ATmega161(L)1228C–AVR–08/02• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0These two bits control the SCK rate of the device configured as a

68ATmega161(L)1228C–AVR–08/02SPI Data Register – SPDRThe SPI Data Register is a read/write register used for data transfer between the Regis-ter File

69ATmega161(L)1228C–AVR–08/02UARTs The ATmega161 features two full-duplex (separate Receive and Transmit Registers)Universal Asynchronous Receiver and

7ATmega161(L)1228C–AVR–08/02ArchitecturalOverviewThe fast-access Register File concept contains 32 x 8-bit general purpose working reg-isters with a s

70ATmega161(L)1228C–AVR–08/02• A new character has been written to UDRn before the stop bit from the previouscharacter has been shifted out. The Shift

71ATmega161(L)1228C–AVR–08/02Data Reception Figure 45 shows a block diagram of the UART Receiver.Figure 45. UART ReceiverThe Receiver front-end logic

72ATmega161(L)1228C–AVR–08/02Figure 46. Sampling Received Data(1)Note: 1. This figure is not valid when the UART speed is doubled. See “Double-speedTr

73ATmega161(L)1228C–AVR–08/02Multi-processorCommunication ModeThe Multi-processor Communication mode enables several Slave MCUs to receive datafrom a

74ATmega161(L)1228C–AVR–08/02UART1 Control and StatusRegisters – UCSR1A• Bit 7– RXC0/RXC1: UART Receive CompleteThis bit is set (one) when a received

75ATmega161(L)1228C–AVR–08/02• Bit 2 – Res: Reserved BitThis bit is reserved bit in the ATmega161 and will always read as zero.• Bit 1– U2X0/U2X1: Dou

76ATmega161(L)1228C–AVR–08/02• Bit 2 – CHR90/CHR91: 9-bit CharactersWhen this bit is set (one), transmitted and received characters are nine bits long

77ATmega161(L)1228C–AVR–08/02Table 24. UBR Settings at Various Crystal FrequenciesBaud Rate1MHz%Error1.8432 MHz%Error2MHz%Error2.4576 MHz%Error2400UBR

78ATmega161(L)1228C–AVR–08/02UART0 and UART1 High ByteBaud Rate Register UBRRHIThe UART Baud Register is a 12-bit register. The four most significant

79ATmega161(L)1228C–AVR–08/02The Baud Rate Generator inDouble UART Speed ModeNote that the baud rate equation is different from the equation on page 7

8ATmega161(L)1228C–AVR–08/02In addition to the register operation, the conventional Memory Addressing modes can beused on the Register File. This is e

80ATmega161(L)1228C–AVR–08/02Table 25. UBR Settings at Various Crystal Frequencies in Double-speed ModeBaud Rate 1.0000 MHz % Error 1.8432 MHz % Error

81ATmega161(L)1228C–AVR–08/02Analog Comparator The Analog Comparator compares the input values on the positive input PB2 (AIN0) andnegative input PB3

82ATmega161(L)1228C–AVR–08/02• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrup

83ATmega161(L)1228C–AVR–08/02Internal VoltageReferenceATmega161 features an internal voltage reference with a nominal voltage of 1.22V. Thisreference

84ATmega161(L)1228C–AVR–08/02Interface to ExternalMemoryWith all the features the external memory interface provides, it is well suited to operateas a

85ATmega161(L)1228C–AVR–08/02• Bits 3..2 EMCUCR – SRW01, SRW00: Wait State Select Bits for Lower PageThe SRW01 and SRW00 bits control the number of wa

86ATmega161(L)1228C–AVR–08/02Figure 49. External Memory with Page SelectFigure 50. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0

87ATmega161(L)1228C–AVR–08/02Figure 51. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)Note: 1. SRWn1 = SRW11 (upper page) or SRW01 (lower

88ATmega161(L)1228C–AVR–08/02Using the ExternalMemory InterfaceThe interface consists of:Port A: multiplexed low-order address bus and data busPort C:

89ATmega161(L)1228C–AVR–08/02I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that

9ATmega161(L)1228C–AVR–08/02Figure 5. Memory MapsA flexible interrupt module has its control registers in the I/O space with an additionalglobal inter

90ATmega161(L)1228C–AVR–08/02Port A pins are tri-stated when a reset condition becomes active, even if the clock is notrunning.Note: 1. n: 7,6…0, pin

91ATmega161(L)1228C–AVR–08/02Port B Port B is an 8-bit bi-directional I/O port.Three I/O memory address locations are allocated for the Port B, one ea

92ATmega161(L)1228C–AVR–08/02Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins.PBn, genera

93ATmega161(L)1228C–AVR–08/02• TXD1/AIN1 – Port B, Bit 3AIN1, Analog Comparator Negative Input. This pin also serves as the negative input ofthe On-ch

94ATmega161(L)1228C–AVR–08/02Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the fig

95ATmega161(L)1228C–AVR–08/02Figure 57. Port B Schematic Diagram (Pin PB2)Figure 58. Port B Schematic Diagram (Pin PB3)DATA BUSDDQQRESETRESETCCWDWPRDM

96ATmega161(L)1228C–AVR–08/02Figure 59. Port B Schematic Diagram (Pin PB4)Figure 60. Port B Schematic Diagram (Pin PB5)DATA BUSDDQQRESETRESETCCWDWPRDM

97ATmega161(L)1228C–AVR–08/02Figure 61. Port B Schematic Diagram (Pin PB6)Figure 62. Port B Schematic Diagram (Pin PB7)DATA BUSDDQQRESETRESETCCWDWPRDM

98ATmega161(L)1228C–AVR–08/02Port C Port C is an 8-bit bi-directional I/O port.Three I/O memory address locations are allocated for the Port C, one ea

99ATmega161(L)1228C–AVR–08/02Note: 1. n:7,6,…0, pin numberPort C Schematics Note that all port pins are synchronized. The synchronization latch is, ho