Rainbow-electronics DS1821 Instrukcja Użytkownika Pobierz pdf (Strona 12)

DS1821

Page 12 of 17

Figure 9 illustrates that the sum of T

INIT

, T

, and T

SAMPLE

must be less than 15 µs for a read time slot.

Figure 10 shows that system timing margin is maximized by keeping T

INIT

and T

as short as possible

and by locating the master sample time during read time slots towards the end of the 15 µs period.

READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8

DETAILED MASTER READ 1 TIMING Figure 9

RECOMMENDED MASTER READ 1 TIMING Figure 10

GND

1-WIRE BUS

µµ

µs

IH of Master

INT

> 1

µµ

µs

Master samples

GND

1-WIRE BUS

µµ

µs

IH of Master

small

INT

small

Master samples

LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)

Bus master pulling low DS1821 pulling low

Resistor pullup

µµ

µs

µµ

µs

GND

1-WIRE BUS

µµ

µs < T

“0” < 120

1 µ

µµ

µs < T

REC

< ∞

DS1821 samples

MIN TYP MA

µµ

µs

µµ

µs

> 1

µµ

µs

MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT

DS1821 samples

MIN TYP MA

GND

1-WIRE BUS

µµ

µs

MASTER READ “0” SLOT MASTER READ “1” SLOT

Master samples

START

OF SLOT

START

OF SLOT

> 1

µµ

µs

1 µ

µµ

µs < T

REC

< ∞

µµ

µs

µµ

µs

µµ

µs

µµ

µs

> 1

µµ

µs

1 2 ... 7 8 9 10 11 12 13 14 15 16 17

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