Rainbow-electronics MAX1427 Instrukcja Użytkownika Pobierz pdf (Strona 4)

MAX1427

15-Bit, 80Msps ADC with -79.3dBFS

Noise Floor for Baseband Applications

4 _______________________________________________________________________________________

Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f

SAMPLE

= 80.019456MHz, an

input frequency of f

= f

SAMPLE

x (6143/32768) = 15.001206MHz, and a frequency bin size of 2442Hz. Close-in (f

±29.3kHz) and low-frequency (DC to 58.6kHz) bins are excluded from the spectrum analysis.

Note 2: Apply the same voltage levels to DV

and DRV

Note 3: Guaranteed by design and characterization.

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 5V, DV

= DRV

= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, C

= 5pF at digital outputs, f

CLK

= 80MHz, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (DV

= DRV

= 3.3V) Figure 4

CLKP/CLKN Duty Cycle

Duty cycle

±5

Effective Aperture Delay t

230

Output Data Delay t

DAT

(Note 3) 2.8 4.1 6.5 ns

Data Valid Delay t

DAV

(Note 3) 5.3 6.3 8.6 ns

Pipeline Latency

LATENCY

Clock

cycles

CLKP Rising Edge to

DATA Not Valid

DNV

(Note 3) 2.5 3.4 5.2 ns

CLKP Rising Edge to

DATA Valid (Guaranteed)

DGV

(Note 3) 3.2 4.4 7.4 ns

DATA Setup Time

(Before DAV Rising Edge)

SETUP

(Note 3)

CLKP

+ 0.2

CLKP

+ 1.7

CLKP

+ 2.8

DATA Hold Time

(After DAV Rising Edge)

HOLD

(Note 3)

CLKN

3.5

CLKN

2.7

CLKN

2.0

POWER REQUIREMENTS

Analog Supply Voltage Range

5 ±3%

Digital Supply Voltage Range

(Note 2)

2.3 to 3.5

Output Supply Voltage Range

DRV

(Note 2)

2.3 to 3.5

Analog Supply Current I

AVCC

377 440

D i g i tal + Outp ut S up p l y C ur r ent

DVCC

CLK

= 80MHz, C

LOAD

= 5pF

35.5

42 mA

Analog Power Dissipation PDISS

1974

1 2 3 4 5 6 7 8 9 ... 17 18

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