MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 3
Note 1: All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and V
EE
without any external
resistance. See Figure 1.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. R
DISC
and R
CL
must be ±1%, 100ppm or better. I
CLASS
includes the IC
bias current and the current drawn by R
DISC
.
Note 6: See the Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V
IN
is at the maximum voltage (MAX5940B only).
Note 8: When the UVLO input voltage is below V
TH,G,UVLO,
the MAX5940B sets the UVLO threshold internally.
Note 9: An input voltage or V
UVLO
glitch below their respective thresholds shorter than or equal to t
OFF_DLY
does not cause the
MAX5940A/MAX5940B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: Guaranteed by design.
Note 11: PGOOD references to OUT while PGOOD references to V
EE
.
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= (GND - V
EE
) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V
EE
, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C. All voltages are referenced to V
EE
, unless otherwise noted.) (Note 1)
Komentarze do niniejszej Instrukcji