Rainbow-electronics AT89C5122 Instrukcja Użytkownika

Rev. 4202E–SCR–06/061 Features• Clock Controller– 80C51 core with 6 clocks per instruction– 8 MHz On-Chip Oscillator– PLL for generating clock to

10 AT8xC5122/234202E–SCR–06/06Figure 5. QFN64 Package Pinout 62 61 60 59 58 63 5756 55 54 53P0.1/AD1P0.3/AD3P0.5/AD5P0.7/AD7D+P4.1/MOSIP4.0/

100 AT8xC5122/234202E–SCR–06/06• Endpoint enableBefore using an endpoint, this one should be enabled by setting the EPEN bit in theUEPCONX registe

101 AT8xC5122/234202E–SCR–06/06• Endpoint FIFO resetBefore using an endpoint, its FIFO should be reset. This action resets the FIFO pointerto its

102 AT8xC5122/234202E–SCR–06/06Read/Write Data FIFORead Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register.Af

103 AT8xC5122/234202E–SCR–06/06Bulk / Interrupt TransactionsBulk and Interrupt transactions are managed in the same way.Bulk/Interrupt OUT Transac

104 AT8xC5122/234202E–SCR–06/06Bulk/Interrupt OUT Transactions in Ping-Pong Mode (Endpoints 6)Figure 56. Bulk / Interrupt OUT Transactions in Pin

105 AT8xC5122/234202E–SCR–06/06If the Host sends more bytes than supported by the endpoint FIFO, the overflow datawon’t be stored, but the USB con

106 AT8xC5122/234202E–SCR–06/06Bulk/Interrupt IN Transactions in Ping-Pong ModeFigure 58. Bulk / Interrupt IN transactions in Ping-Pong modeAn en

107 AT8xC5122/234202E–SCR–06/06Control TransactionsSetup Stage The DIR bit in the UEPSTAX register should be at 0.Receiving Setup packets is the s

108 AT8xC5122/234202E–SCR–06/06Isochronous TransactionsIsochronous OUT Transactions in Standard ModeAn endpoint should be first enabled and config

109 AT8xC5122/234202E–SCR–06/06If the Host sends more bytes than supported by the endpoint FIFO, the overflow datawon’t be stored, but the USB con

11 AT8xC5122/234202E–SCR–06/06Low Pin Count Package DescriptionAT8xC5122 and AT83C5123 versionsFigure 6. PLCC28 Package PinoutAT83C5123 version F

110 AT8xC5122/234202E–SCR–06/06MiscellaneousUSB Reset The EORINT bit in the USBINT register is set by hardware when a End of Reset hasbeen detecte

111 AT8xC5122/234202E–SCR–06/06Suspend/Resume ManagementSuspend The Suspend state can be detected by the USB controller if all the clocks are enab

112 AT8xC5122/234202E–SCR–06/06Figure 59. Example of a Suspend/Resume ManagementUpstream Resume A USB device can be allowed by the Host to send a

113 AT8xC5122/234202E–SCR–06/06Figure 60. Example of REMOTE WAKEUP ManagementUSB Controller InitDetection of a SUSPEND stateSPINTSet RMWUPE Suspe

114 AT8xC5122/234202E–SCR–06/06Detach Simulation In order to be re-enumerated by the Host, the AT8xC5122/23 has the possibility to sim-ulate a DET

115 AT8xC5122/234202E–SCR–06/06USB Interrupt SystemInterrupt System PrioritiesFigure 63. USB Interrupt Control SystemInterrupt Control System As

116 AT8xC5122/234202E–SCR–06/06Figure 64. USB Interrupt Control Block DiagramTXCMPUEPSTAX.0RXOUTB0UEPSTAX.1RXSETUPUEPSTAX.2STLCRCUEPSTAX.3EPXIEUE

117 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 0000 0000bTable 64. USB Global Control Register - USBCON (S:BCh)76 5 43210USBE SUSPCLK SDRM

118 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 65. USB Global Interrupt Register - USBINT (S:BDh)76543210- - WUPCPU EORINT SOFINT -

119 AT8xC5122/234202E–SCR–06/06Reset Value = 0001 0000bReset Value = 1000 0000bTable 66. USB Global Interrupt Enable Register - USBIEN (S:BEh)- -

12 AT8xC5122/234202E–SCR–06/06Figure 8. QFN32 Package Pinout CIOQFN32P3.1/TxDCCLKP5.0CC4DVCCCC8XTAL1LIVCCP3.7/LED3CVCCCVSSP3.6/LED2CRSTP1.2/CPRES

120 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bReset Value = 1000 0000b when UEPNUM = 0Reset Value = 0000 0000b otherwiseTable 68. USB En

121 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPN

122 AT8xC5122/234202E–SCR–06/06Reset Value = XXXX XXXXbReset Value = 0000 0000bTable 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register

123 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)76543210- EP6RST EP5RST EP4RST

124 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)76543210- EP6INT EP5IN

125 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 75. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h)76543210- EP6INTE EP5INTE

126 AT8xC5122/234202E–SCR–06/06Serial I/O Port The serial I/O port in the AT8xC5122/23 is compatible with the serial I/O port in the80C52.The I/O

127 AT8xC5122/234202E–SCR–06/06Figure 67. UART Timings in Modes 2 and 3Automatic Address RecognitionThe automatic address recognition feature is

128 AT8xC5122/234202E–SCR–06/06The SADEN byte is selected so that each slave may be addressed separately.For slave A, bit 0 (the LSB) is a don’t c

129 AT8xC5122/234202E–SCR–06/06Figure 68. Timer 1 Baud Rate Generator Block DiagramInternal Baud Rate Generator When using the Internal Baud Rate

13 AT8xC5122/234202E–SCR–06/06Pin DescriptionTable 2. Pin Description PortVQFP64VQFP32PLCC68PLCC28QFN64QFN32InternalPowerSupply ESD I/OReset Leve

130 AT8xC5122/234202E–SCR–06/06Figure 70. Serial I/O Port Block Diagram (Mode 0)Transmission (Mode 0) To start a transmission mode 0, write to SC

131 AT8xC5122/234202E–SCR–06/06Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable.As shown in Figure 73, the select

132 AT8xC5122/234202E–SCR–06/06Figure 76. Data Frame Format (Mode 1)Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data fra

133 AT8xC5122/234202E–SCR–06/06Baud Rate Selection (Modes 1 and 3)In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Intern

134 AT8xC5122/234202E–SCR–06/06Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 ofth

135 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 0000 0000b (Bit addressable)Table 77. Serial Control Register - SCON (98h)76543210FE/SM0 SM

136 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = XXXX XXXXbReset Value = 0000 0000bTable 82. Baud Rat

137 AT8xC5122/234202E–SCR–06/06Serial Port Interface (SPI)Only for AT8xC5122.The Serial Peripheral Interface module (SPI) which allows full-duplex

138 AT8xC5122/234202E–SCR–06/06Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must staylow for any

139 AT8xC5122/234202E–SCR–06/06Functional Description Figure 84 shows a detailed structure of the SPI module.Figure 84. SPI Module Block DiagramO

14 AT8xC5122/234202E–SCR–06/06P2.6 49 - 62 - 49 - VCC 2KV I/O 1 A14 Port51 Push-pull KB_OUTInput WPUP2.7 46 - 57 - 46 - VCC 2KV I/O 1 A15 Port51 P

140 AT8xC5122/234202E–SCR–06/06Figure 85. Full-duplex Master-Slave InterconnectionMaster Mode The SPI operates in Master mode when the Master bit

141 AT8xC5122/234202E–SCR–06/06Figure 86. Data Transmission Format (CPHA = 0)Figure 87. Data Transmission Format (CPHA = 1)As shown in Figure 86

142 AT8xC5122/234202E–SCR–06/06sions (Figure 88). This format may be preferable in systems having only one Master andonly one Slave driving the MI

143 AT8xC5122/234202E–SCR–06/06Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS isinconsistent with the mode of th

144 AT8xC5122/234202E–SCR–06/06Reset Value = 00010100bTable 85. Serial Peripheral Control Register - SPCON (C3h)76543210SPR2 SPEN SSDIS MSTR CPOL

145 AT8xC5122/234202E–SCR–06/06Serial Peripheral Status Register (SPSTA)The Serial Peripheral Status Register contains flags to signal the followi

146 AT8xC5122/234202E–SCR–06/06Serial Peripheral DATa Register (SPDAT)The Serial Peripheral Data Register (Table 87) is a read/write buffer for th

147 AT8xC5122/234202E–SCR–06/06Timers/Counters The AT8xC5122D implements two general-purpose, 16-bit Timers/Counters. Althoughthey are identified

148 AT8xC5122/234202E–SCR–06/06For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented bythe selected input. Setting GATE0

149 AT8xC5122/234202E–SCR–06/06Figure 92. Timer/Counter x (x = 0 or 1) in Mode 1Figure 93. Mode 1 Overflow Period FormulaMode 2 (8-bit Timer wit

15 AT8xC5122/234202E–SCR–06/06P5.5 7 - 16 - 7 - VCC 2KV I/O 1 KB5 Port51 Push-pullInput WPDInput WPUP5.6 5 - 14 - 5 - VCC 2KV I/O 1 KB6 Port51 Pus

150 AT8xC5122/234202E–SCR–06/06Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timers (seeFigur

151 AT8xC5122/234202E–SCR–06/06• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, u

152 AT8xC5122/234202E–SCR–06/06Registers Timer/Counter Control RegisterReset Value = 0000 0000bTable 88. TCON (S:88h)76543210TF1 TR1 TF0 TR0 IE1

153 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 89. Timer/Counter Mode Control Register - TMOD (S:89h)76543210GATE1 C/T1# M11 M01 GA

154 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 90. Timer 0

155 AT8xC5122/234202E–SCR–06/06Keyboard Interface Only for AT8xC5122.Introduction The AT8xC5122/23 implements a keyboard interface allowing the co

156 AT8xC5122/234202E–SCR–06/06Power Reduction Mode P5 inputs allow exit from idle and power-down modes as detailed in Section "Power-Down Mo

157 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 95. Keyboard Input Enable Register - KBE (9Dh)76543210KBE7 KBE6 KBE5 KBE4 KBE3 KBE2

158 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 96. Keyboard Level Selector Register - KBLS (9Ch)76543210KBLS7 KBLS6 KBLS5 KBLS4 KBL

159 AT8xC5122/234202E–SCR–06/06Interrupt SystemIntroduction The AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used

16 AT8xC5122/234202E–SCR–06/06PSEN 15 - 24 - 15 - VCC OProgram Strobe Enable: The read strobe to external program memory. When executing code from

160 AT8xC5122/234202E–SCR–06/06Figure 100. Interrupt Control SystemIE0SPI SMART CARDINT1CPRESRXDRXEN01IE11001PRESITISEL.0ISEL.4RXITOEENISEL.2OELE

161 AT8xC5122/234202E–SCR–06/06INT1 Interrupt Vector The INT1 interrupt is multiplexed with the following three inputs: • INT1 : Standard 8051 int

162 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 0000 0000b (Bit addressable)Table 98. Interrupt Enable Register 0 - IEN0 (A8h)76543210EA -

163 AT8xC5122/234202E–SCR–06/06Reset Value = X0XX 00X0b (Bit addressable)Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC512276543210

164 AT8xC5122/234202E–SCR–06/06Reset Value = X0XX 0XXXb (Bit addressable)Reset Value = X000 0000b (Bit addressable)Table 100. Interrupt Enable Re

165 AT8xC5122/234202E–SCR–06/06Reset Value = X000 0000b (Not bit addressable)Table 102. Interrupt Priority High Register 0 - IPH0 (B7h)76543210-

166 AT8xC5122/234202E–SCR–06/06Reset Value = X00X 00X0b (Bit addressable)Table 103. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC51227

167 AT8xC5122/234202E–SCR–06/06Reset Value = X0XX 0XXXb (Bit addressable)Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT83C51237

168 AT8xC5122/234202E–SCR–06/06Reset Value = XXXX X000b (Not bit addressable)Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC

169 AT8xC5122/234202E–SCR–06/06Reset Value = X0XX 0XXXb (Not bit addressable)Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C

17 AT8xC5122/234202E–SCR–06/06Typical ApplicationsRecommended External componentsAll the external components described in the figure and table bel

170 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 107. Interrupt Enable Register - ISEL (S:A1h)76543210CPLEV - PRESIT RXIT OELEV OEEN

171 AT8xC5122/234202E–SCR–06/06Interrupt Sources and VectorsNote: 1. Only fot AT8xC5122Table 108. Interrupt VectorsInterrupt SourcePolling Priori

172 AT8xC5122/234202E–SCR–06/06Microcontroller ResetIntroduction The internal reset is used to start up (cold reset) or to re-start (warm reset) t

173 AT8xC5122/234202E–SCR–06/06Power On Reset (POR) The role of the POR is to monitor the power supply rise of the microcontroller core andrelease

174 AT8xC5122/234202E–SCR–06/06Figure 102. Static behaviour of POR and PFDFigure 103. Dynamic behaviour of POR and PFDVCoretInternalVPFDPVPFDM10

175 AT8xC5122/234202E–SCR–06/06Reset pin As explained in the POR section there is no need to use the reset pin as the internalreset function at po

176 AT8xC5122/234202E–SCR–06/06Reset Controlled by an External Superviser DeviceAs the reset pin can be forced in output by the Watch-Dog timer (W

177 AT8xC5122/234202E–SCR–06/06Watchdog Timer The AT8xC5122/23 microcontrollers contain a powerfull programmable hardwareWatchdog Timer (WDT) that

178 AT8xC5122/234202E–SCR–06/06Reset Value = XXXX X000bThe three lower bits (S0, S1, S2) located into WDTPRG register enables to program theWDT du

179 AT8xC5122/234202E–SCR–06/06Table 111. Timeout value for FCK_WD = 24 MHz / X2Reset Value = XXXX XXXXbThe WDTRST register is used to reset / en

18 AT8xC5122/234202E–SCR–06/06USB Keyboard with Smart Card Reader Using the AT8xC5122 and AT89C5122DS VersionsLEDxVCCKB1KB2KB3KB4KB5KB6KB7R19R18R1

180 AT8xC5122/234202E–SCR–06/06Power ManagementBefore activating the Idle Mode or Power Down Mode, the CPU clock must be switchedto on-chip oscill

181 AT8xC5122/234202E–SCR–06/06Figure 109. Power-down Exit WaveformExit from power-down by reset redefines all the SFRs, exit from power-down by

182 AT8xC5122/234202E–SCR–06/06USB InterfaceSuspend The Suspend state can be detected by the USB controller if all the clocks are enabledand if th

183 AT8xC5122/234202E–SCR–06/06Figure 110. Example of a Suspend/Resume ManagementSmart Card InterfaceEntering in Power-down Mode In order to redu

184 AT8xC5122/234202E–SCR–06/06Keyboard Interface The keyboard interface applies only to AT8xC5122 version.Entering in Power-down Mode In order to

185 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 00X1 0000bPower-off flag reset value will be 1 only after a power on (cold reset). A warm re

186 AT8xC5122/234202E–SCR–06/06Electrical Characteristics Absolute Maximum RatingsDC ParametersTA = -40 to +85°C; VSS = 0 V, FCK_CPU= 0 to 24 MHz

187 AT8xC5122/234202E–SCR–06/06RRSTInternal reset pull-up resistor 5 10 30 kΩIPDPower down consumption60µA40µA200µA200µAVcc = 5.5VVcc = 3.6VICCIDL

188 AT8xC5122/234202E–SCR–06/06ICC Current Test Conditions Figure 111. Power Down ModeFigure 112. Active and Idle ModeLED’sNote: 1. (TA = -20°C

189 AT8xC5122/234202E–SCR–06/06Smart Card InterfaceCard VCC 5V (for IEC7816-3 Class A cards)Symbol Parameter Min Typ Max Unit Test ConditionsVcc P

19 AT8xC5122/234202E–SCR–06/06USB Smart Card Reader Using the AT83C5123 VersionLEDxVCCGNDRSTOptionalCapacitorGNDGNDC1EAGNDGNDC8C9VCCVCCVCC AVCCXTA

190 AT8xC5122/234202E–SCR–06/06Notes: 1. Test conditions, Capacitor 10 µF, Inductance 10 µH.2. Ceramic X7R, SMD type capacitor with minimum ESR or

191 AT8xC5122/234202E–SCR–06/06Note: 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation. Note: 1. The voltage

192 AT8xC5122/234202E–SCR–06/06USB Interface Figure 113. USB InterfaceSymbol Parameter Min Typ(5)Max UnitVREFUSB Reference Voltage 3.0 3.6 VVIHIn

193 AT8xC5122/234202E–SCR–06/06AC ParametersExplanation of the AC SymbolsEach timing symbol has 5 characters. The first character is always a “T”

194 AT8xC5122/234202E–SCR–06/06External Program Memory Read CycleTable 115. AC Parameters for a Variable ClockSymbol TypeStandard clock X2 Clock

195 AT8xC5122/234202E–SCR–06/06External Data Memory CharacteristicsTable 116. Symbol DescriptionSymbol ParameterTRLRHRD Pulse WidthTWLWHWR Pulse

196 AT8xC5122/234202E–SCR–06/06Table 117. AC Parameters for a Variable Clock (warning x value differ from AT89C51RD2)External Data Memory Write C

197 AT8xC5122/234202E–SCR–06/06External Data Memory Read CycleSerial Port Timing - Shift Register ModeTable 118. Symbol Description (F = 40 MHz)T

198 AT8xC5122/234202E–SCR–06/06Shift Register Timing WaveformExternal Clock Drive Characteristics (XTAL1) Table 120. AC ParametersExternal Clock

199 AT8xC5122/234202E–SCR–06/06Float WaveformsFor timing purposes as port pin is no longer floating when a 100 mV change from loadvoltage occurs a

2 AT8xC5122/234202E–SCR–06/06Reference Documents The user must get the following additionnal documents which are not included but whichcomplete th

20 AT8xC5122/234202E–SCR–06/06Memory Organization The AT8xC5122/23 devices have separated address spaces for Program and DataMemory, as shown in F

200 AT8xC5122/234202E–SCR–06/06This diagram indicates when signals are clocked internally. The time it takes the signalsto propagate to the pins,

201 AT8xC5122/234202E–SCR–06/06Packaging InformationOrdering InformationStandardPart NumberLead free/ RoHSPart NumberMemory Size (bytes)Supply Vol

202 AT8xC5122/234202E–SCR–06/06Note: 1. Check avaibility with sales officeAT89C5122DS-RDVIM AT89C5122DS-RDTUM 32K FLASH 3.0 - 5.5 Industrial 48 MH

203 AT8xC5122/234202E–SCR–06/06Mechanical DimensionsPLCC28 Package

204 AT8xC5122/234202E–SCR–06/06VQFP64 Package

205 AT8xC5122/234202E–SCR–06/06PLCC68 Package

206 AT8xC5122/234202E–SCR–06/06VQFP32 Package

207 AT8xC5122/234202E–SCR–06/06QFN32 Package

208 AT8xC5122/234202E–SCR–06/06QFN64 Package

209 AT8xC5122/234202E–SCR–06/06Datasheet Revision HistoryChanges from 4202A to 4202B1. Product AT8xEC5122 added.2. Products AT83C5123 and AT83EC51

21 AT8xC5122/234202E–SCR–06/06Data Memory ManagamentAll device versions implements :- 256 Bytes of RAM to increase data parameter handling and hig

2104202E–SCR–06/06AT8xC5122/23Table of ContentsFeatures ...

2114202E–SCR–06/06AT8xC5122/23Definitions... 6

2124202E–SCR–06/06AT8xC5122/23Registers... 162

Printed on recycled paper.4202E–SCR–06/06© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, are registered tradema

22 AT8xC5122/234202E–SCR–06/06An access to external XRAM memory locations higher than the accessible size of thememory (roll-over feature) will be

23 AT8xC5122/234202E–SCR–06/06Figure 11. Use of Dual Pointera. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

24 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 0XXX X000bTable 5. Auxiliary Register - AUXR (8Eh)76543210DPU - - - XRS0 EXTRAM AOBit Number

25 AT8xC5122/234202E–SCR–06/06Table 6. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122Reset Value = XX1X XX0X0b (Not bit addressable)Table 7. A

26 AT8xC5122/234202E–SCR–06/06Reset Value = XXXX 0XXXbAT8xC5122’s CRAM and E2PROM VersionsThe AT8xC5122’s CRAM and E2PROM versions implements :- 3

27 AT8xC5122/234202E–SCR–06/06When pin EA =1 and after the reset, the MCU begins the execution of the embeddedbootloader from location F800h of th

28 AT8xC5122/234202E–SCR–06/06Using CRAM Memory The CRAM is a read / write volatile memory that is mapped in the program memoryspace. Then when th

29 AT8xC5122/234202E–SCR–06/06Figure 13. AT8xC5122’s CRAM and E2PROM VersionsReset@<0000>EA = 0PROGRAM EXTERNALPROGRAMPSENReset@00007FFF800

3 AT8xC5122/234202E–SCR–06/06Product Description AT8xC5122/23 products are high-performance CMOS derivatives of the 80C51 8-bitmicrocontrollers de

30 AT8xC5122/234202E–SCR–06/06AT8xC5122’s ROM VersionThe AT8xC5122’s ROM version implements :- 32 K of ROM mapped from 0000h to 7FFFh in which is

31 AT8xC5122/234202E–SCR–06/06Figure 14. AT8xC5122’s ROM VersionPROGRAM MEMORY(Read only)00007FFFFFFFEA=1INTERNAL32K ROMEA=0EXTERNALEXTERNALRESET

32 AT8xC5122/234202E–SCR–06/06AT83C5123 Version The AT83C5123 device is a low pin count version of the AT8xC5122.The ROM version implements :- 30

33 AT8xC5122/234202E–SCR–06/06Special Function Registers (SFR’s)Introduction The Special Function Registers (SFRs) of the AT8xC5122/23 can be rank

34 AT8xC5122/234202E–SCR–06/06AT8xC5122 VersionNotes: 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in.Bitaddre

35 AT8xC5122/234202E–SCR–06/06AT83C5123 VersionNotes: 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in.Bitaddre

36 AT8xC5122/234202E–SCR–06/06SFR’s DescriptionNote: 1. Only for AT8xC5122Note: 1. Only for AT8xC5122Table 10. C51 Core SFRsMnemonicAddName 76543

37 AT8xC5122/234202E–SCR–06/06Table 13. Timers SFRsMnemonicAddName 76543210TH0 8Ch Timer/Counter 0 High byte TH0TL0 8Ah Timer/Counter 0 Low byte

38 AT8xC5122/234202E–SCR–06/06Note: 1. Only for AT8xC5122IPH0 B7hInterrupt Priority Control High 0PSH PT1HPX1HPT0HPX0HIPL1 B2hInterrupt Priority C

39 AT8xC5122/234202E–SCR–06/06Note: 1. Only for AT8xC5122Note: 1. Only for AT8xC5122Notes: 1. Only for AT8xC5122SCICLK C1hSmart Card Frequency Pre

4 AT8xC5122/234202E–SCR–06/06Note: The PLCC28 pinout is common to AT8xC5122 and AT83C5123 productsTable 1. Product versionsFeatures AT83C5122 AT8

40 AT8xC5122/234202E–SCR–06/06 Note: 1. Only for AT8xC5122UEPIEN C2hUSB Endpoint Interrupt EnableEP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE E

41 AT8xC5122/234202E–SCR–06/06Clock Controller The clock controller is based on an on-chip oscillator feeding an on-chip Phase LockLoop (PLL). All

42 AT8xC5122/234202E–SCR–06/06Phase Lock Loop (PLL)PLL Description The AT8xC5122/23’s PLL is used to generate internal high frequency clock synchr

43 AT8xC5122/234202E–SCR–06/06Figure 19. PLL Programming FlowClock Tree Architecture The clock controller outputs several different clocks as sho

44 AT8xC5122/234202E–SCR–06/06Figure 20. Clock Tree DiagramCPU and Peripheral Clocks Two clocks sources are available for CPU and peripherals:– o

45 AT8xC5122/234202E–SCR–06/06The CPU and peripherals clocks frequencies are defined in the table below.X1 and X2 Modes Use of on-chip oscillatorW

46 AT8xC5122/234202E–SCR–06/06Figure 21. X1 modeWhen the X1 mode is selected, the CPU and Peripherals work at 8Mhz / X1Figure 22. X2 modeWhen th

47 AT8xC5122/234202E–SCR–06/06Use of PLL Clock When the CPU clock is fed by the PLL, the X2 mode is forbidden. The bit X2 mustalways remain cleare

48 AT8xC5122/234202E–SCR–06/06SCIB Clock The Smart Card Interface Block (SCIB) uses two clocks : – The first one, CK_IDLE, is the peripheral clock

49 AT8xC5122/234202E–SCR–06/06If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work.If the CK_CPU >= 6* CK_ISO, the programmer must take care

5 AT8xC5122/234202E–SCR–06/06AT8xC5122 Block DiagramAT83C5123 Block DiagramDC/DCConverterLICVCCCVSSUARTInterfaceTxDRxD16-BITTIMERST[0-1]InterruptC

50 AT8xC5122/234202E–SCR–06/06USB Interface Clock The USB Interface uses two clocks : – The first one is the CPU clock used for the interface with

51 AT8xC5122/234202E–SCR–06/06Reset Value = X0X0 X000bTable 26. Clock Configuration Register 0 - CKCON0 (S:8Fh)76543210-WDX2- SIX2 - T1X2T0X2X2Bi

52 AT8xC5122/234202E–SCR–06/06Reset Value = XXXX XXX0bReset Value = 0000 0000bReset Value = 0000 0000bTable 27. Clock Configuration Register 1 -

53 AT8xC5122/234202E–SCR–06/06I/O Port DefinitionPorts vs Packages Table 30. I/O Number vs PackagesPort 0 Port 0 has the following functions: – D

54 AT8xC5122/234202E–SCR–06/06Port 1 Port 1 has the following functions: – Default function : Only Port 1.2, P1.6 and P1.7 are standard I/O’s; the

55 AT8xC5122/234202E–SCR–06/06Port 3 Port 3 has the following functions: – Default function: Port 3 is an 8-bit I/O port. – Alternate functions: s

56 AT8xC5122/234202E–SCR–06/06Port 4 Port 4 has the following functions: – Default function: Port 4 is an 6-bit I/O port. – Alternate functions: s

57 AT8xC5122/234202E–SCR–06/06Port ConfigurationStandard I/O P0 The P0 port is described in Figure 23.Figure 23. Standard Input/Output PortQuasi

58 AT8xC5122/234202E–SCR–06/06The “Port51” is described in Figure 24.Figure 24. Quasi Bi-directional PortPush-pull Output Configuration The push-

59 AT8xC5122/234202E–SCR–06/06Figure 26. Input with Pull-upInput with Weak Pull-down ConfigurationThe input with pull-down (input WPD) configurat

6 AT8xC5122/234202E–SCR–06/06PinoutHigh Pin Count Package DescriptionAT8xC5122 version Figure 1. VQFP64 Package Pinout 62 61 60 59 58 63 575

60 AT8xC5122/234202E–SCR–06/06Figure 29. LED Source CurrentNotes: 1. When switching a low level, LEDCTRL device has a permanent current of about

61 AT8xC5122/234202E–SCR–06/06RegistersReset Value = 0000 0x00bReset Value = 00xx 0xxxbTable 36. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122

62 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bReset Value = xxxx 00xxbTable 38. Port Mode Register 1 - PMOD1 (84h) for AT8xC512276543210P

63 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 40. LED Port Control Register 0 - LEDCON0 (F1h)76543210LED3.1

64 AT8xC5122/234202E–SCR–06/06Smart Card Interface Block (SCIB)The SCIB provides all signals to interface directly with a smart card. The complian

65 AT8xC5122/234202E–SCR–06/06Block DiagramThe Smart Card Interface Block diagram is shown Figure 30: Figure 30. SCIB Block DiagramDefinitions Th

66 AT8xC5122/234202E–SCR–06/06ATR Answer To Reset. Response from the ICC to a Reset initiated by the TerminalF and D F = Clock Rate Conversion Fa

67 AT8xC5122/234202E–SCR–06/06IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMVsays this procedure is mandatory

68 AT8xC5122/234202E–SCR–06/06The Guard Time counter is an 9 bit counter It is initialized at 001h at the start of a trans-mission by the Terminal

69 AT8xC5122/234202E–SCR–06/06Figure 32. Block Guard Time.Figure 33. Guard Time and Block Guard Time countersTo illustrate the use of Guard Time

7 AT8xC5122/234202E–SCR–06/06Figure 2. PLCC68 Package Pinout (for engineering purpose only)18171615141311P0.1/AD1P0.3/AD3P0.5/AD5P0.7/AD7D+P4.1/M

70 AT8xC5122/234202E–SCR–06/06When the WT counter times out, an interrupt is generated and the SCIB function islocked: reception and emission are

71 AT8xC5122/234202E–SCR–06/06Figure 35. T=0 modeIn T=1 protocol : The maximum interval between the leading edge of the start bit of 2consecutive

72 AT8xC5122/234202E–SCR–06/06Power-on and Power-off FSM The Power-on Power-off Finite State Machine (FSM) applies the signals on the smartcard in

73 AT8xC5122/234202E–SCR–06/06Removal of the smart card will automatically start the power off sequence as describedin Figure 39.The SCIB deactiva

74 AT8xC5122/234202E–SCR–06/06Additional FeaturesClock The CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816.The CK_ISO can be pro

75 AT8xC5122/234202E–SCR–06/06Transmit / Receive Buffer The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into /from

76 AT8xC5122/234202E–SCR–06/06Figure 43. CharacterTransmission DiagramSCIBUFTransmittedCharacterShift RegisterI/O pinSCTBESCTCSCISR registerSCTBI

77 AT8xC5122/234202E–SCR–06/06Figure 44. Character Reception DiagramSCIB Reset The SCICR register contains a reset bit. If set, this bit generate

78 AT8xC5122/234202E–SCR–06/06Alternate Card A second card named ‘Alternate Card’ can be controlled.The Clock signal CCLK1 can be adapted to the X

79 AT8xC5122/234202E–SCR–06/06Reset Value = 0000 0000bTable 44. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = 1)76543210RESET CARD

8 AT8xC5122/234202E–SCR–06/06Figure 3. QFN64 Package Pinout 62 61 60 59 58 63 5756 55 54 53P0.1/AD1P0.3/AD3P0.5/AD5P0.7/AD7D+P4.1/MOSIP4.0/M

80 AT8xC5122/234202E–SCR–06/06Reset Value = 0X00 0000bTable 45. Smart Card Contacts Register - SCCON (S:ACh, SCRS=0)76543210CLK - CARDC8 CARDC4 C

81 AT8xC5122/234202E–SCR–06/06 Reset Value = 1000 0000bTable 46. Smart Card UART Interface Status Register -SCISR (S:ADh, SCRS=0)76 5 4 3210SCTBE

82 AT8xC5122/234202E–SCR–06/06 Reset Value = 0X00 0000bNote: 1) In case of multiple interrupts occuring at the same time (sampled by the same edge

83 AT8xC5122/234202E–SCR–06/06Reset Value = 0X00 0000bTable 48. Smart Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS=1)765 4 3210ESCT

84 AT8xC5122/234202E–SCR–06/06Reset Value = X000 1000bReset Value = 0000 0000bTable 49. Smart Card Selection Register - SCSR (S:ABh)76543210- BGT

85 AT8xC5122/234202E–SCR–06/06 Reset Value = 0XXX X001b Reset Value = 0111 0100bTable 51. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1)76543

86 AT8xC5122/234202E–SCR–06/06 Reset Value = 0000 1100b Reset Value = XXXX XXX0b Reset Value = 0000 0000bTable 53. Smart Card Transmit Guard Time

87 AT8xC5122/234202E–SCR–06/06 Reset Value = 0000 0000b Reset Value = 0010 0101b Reset Value = 1000 0000bTable 56. Smart Card Character/Block Wai

88 AT8xC5122/234202E–SCR–06/06Reset Value = 0X10 1111b (default value for a divider by two)DC/DC Converter The Smart Card voltage (CVCC) is suppli

89 AT8xC5122/234202E–SCR–06/06mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflowcontroller is operating, the ICARDOV

9 AT8xC5122/234202E–SCR–06/06AT89C5122DS version Figure 4. VQFP64 Package Pinout 62 61 60 59 58 63 5756 55 54 53P0.1/AD1P0.3/AD3P0.5/AD5P0.7

90 AT8xC5122/234202E–SCR–06/06Figure 46. Card Vcc = 1.8V Initialization ProcedureMode RegulationDCCKPS[7]=1VCARDOK=1Set Timeout to 3 msTimeoutExp

91 AT8xC5122/234202E–SCR–06/06Figure 47. Card Vcc = 3V Initialization ProcedureMode RegulationDCCKPS[7]=1VCARDOK=1Set Timeout to 3 msTimeoutExpir

92 AT8xC5122/234202E–SCR–06/06Procedure for CVcc = 5volts The DC/DC pump mode must be selected (MODE = 0 in DCCKPS register). Thedetailed procedur

93 AT8xC5122/234202E–SCR–06/06advised to decrement the BOOST[1:0] bits to restore the overflow current to its normalor desired value.Monitoring Pr

94 AT8xC5122/234202E–SCR–06/06DC/DC Converter registerReset Value = 0000 0000bTable 61. DC/DC Converter Control Register - DCCKPS (S:BFh)76543210

95 AT8xC5122/234202E–SCR–06/06USB Controller The AT8xC5122D implements a USB device controller supporting Full Speed datatransfer. In addition to

96 AT8xC5122/234202E–SCR–06/06The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes,which is the size of the FIFO im

97 AT8xC5122/234202E–SCR–06/06Figure 50. SIE Block DiagramFunction Interface Unit (UFI) The Function Interface Unit provides the interface betwee

98 AT8xC5122/234202E–SCR–06/06Figure 52. Minimum Intervention from the USB Device FirmwareOUT Transactions:HOSTUFIC51OUT DATA0 (n Bytes)ACKEndpoi

99 AT8xC5122/234202E–SCR–06/06ConfigurationGeneral Configuration • USB controller enableBefore any USB transaction, the 48 MHz required by the USB