
179
AT8xC5122/23
4202E–SCR–06/06
Table 111. Timeout value for F
CK_WD
= 24 MHz / X2
Reset Value = XXXX XXXXb
The WDTRST register is used to reset / enable the WDT by writing 1EH then E1H in
sequence.
S2 S1 S0 Timeout for F
CK_WD
= 24 MHz / X2
000 4.10 ms
001 8.19 ms
0 1 0 16.38 ms
0 1 1 32.77 ms
1 0 0 65.54 ms
1 0 1 131.07 ms
1 1 0 262.14 ms
1 1 1 524.29 ms
Table 112. Watchdog Timer Enable register (Write Only) - WDTRST (A6h)
76543210
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