Rainbow-electronics BR24L32FV-W Instrukcja Użytkownika Pobierz pdf (Strona 10)

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

10/25

Byte write

SDA

LINE

SLAVE

ADDRESS

10 01

DATA

Fig.8 BYTE WRITE CYCLE TIMING

1st WORD

ADDRESS

2nd WORD

ADDRESS

∗Don't care

∗∗∗∗

A0A1A2

•

By using this command, the data is programmed into the indicated word address.

•

When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory

array.

Page write

Fig.9 PAGE WRITE CYCLE TIMING

SDA

LINE

SLAVE

ADDRESS

10 01

DATA (n)

DATA (n+31)

1st WORD

ADDRESS (n)

2nd WORD

ADDRESS (n)

∗Don't care

∗∗∗∗

A0A1A2

•

This device is capable of thirty-two byte Page Write operation.

•

When two or more byte data are inputted, the five low order address bits are internally incremented by one after the

receipt of each word. The seven higher order bits of the address (WA11 to WA5) remain constant.

•

If the master transmits more than thirty-two words, prior to generating the STOP condition, the address counter will

“roll over”, and the previous transmitted data will be overwritten.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 24 25

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