Rainbow-electronics AT75C310 Instrukcja Użytkownika

1Features• ARM7TDMI™ ARM® Thumb® Processor Core• Two 16-bit Fixed-point OakDSPCore® Cores• 256 x 32-bit Boot ROM• 88K Bytes of Integrated Fast RAM for

AT75C31010ClockingThe AT75C310 uses an external 16 MHz crystal (XCLK)and two on-chip PLLs to generate the internal clocks. OnePLL generates a 96 MHz c

AT75C310100TC Interrupt Mask Register Register Name: TC_IMRAccess Type: Read-only • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disa

AT75C310101SPI: Serial Peripheral InterfaceThe serial peripheral interface provides communicationwith external devices in master or slave mode. It als

AT75C310102Master ModeIn master mode, the SPI controls data transfers to and fromthe slave(s) connected to the SPI bus. The SPI drives thechip select(

AT75C310103Figure 22. Functional Flow Diagram in Master ModeSPI EnableTDREPS1001110Same PeripheralNew peripheralNPCS = SP_TDR(PCS) NPCS = SP_MR(PCS)D

AT75C310104Figure 23. SPI in Master Mode01SP_MR(ACLK32)ACLKACLK/32SPCK Clock GeneratorSP_CSRx[15:0]SRQMODFTDRERDRFOVRESPIENS01SP_MR(PS)PCSSP_RDRSeria

AT75C310105Slave ModeIn slave mode, the SPI waits for NPCSS to go active lowbefore receiving the serial clock from an external master.In slave mode, C

AT75C310106Data TransferFigure 25, Figure 26 and Figure 27 show examples of data transfers.Figure 25. SPI Transfer Format (NCPHA Equals One, Eight Bi

AT75C310107Figure 27. Programmable Delays (DLYBCS, DLYBS and DLYBCT)Clock GenerationIn master mode, the SPI master clock is either ACLK orACLK/32 as

AT75C310108SPI Control Register Register Name: SP_CRAccess Type: Write-only• SPIEN: SPI Enable0 = No effect.1 = Enables the SPI to transfer and receiv

AT75C310109SPI Mode RegisterRegister Name: SP_MRAccess Type: Read/write • MSTR: Master/Slave Mode0 = SPI is in slave mode. 1 = SPI is in master mode.

AT75C31011Boot ModeWhen the reset pin is deasserted, i.e., when the AT75C310exits from reset state, the NDSRA/BOOTN pin is sampled.If NDSRA/BOOTN is h

AT75C310110• PCS: Peripheral Chip SelectThis field is only used if Fixed Peripheral Select is active (PS=0).If PCSDEC=0: PCS = xxx0 NPCS[3:0] = 1110PC

AT75C310111SPI Transmit Data RegisterRegister Name: SP_TDRAccess Type: Write-only• TD: Transmit Data Data that is to be transmitted by the SPI interfa

AT75C310112SPI Status Register Register Name: SP_SRAccess Type: Read-only• RDRF: Receive Data Register Full0 = No data has been received since the las

AT75C310113SPI Interrupt Enable Register Register Name: SP_IERAccess Type: Write-only• RDRF: Receive Data Register Full Interrupt Enable0 = No effect.

AT75C310114• MODF: Mode Fault Interrupt Disable0 = No effect.1 = Disables the Mode Fault Interrupt. • OVRES: Overrun Error Interrupt Disable0 = No eff

AT75C310115SPI Chip Select RegisterRegister Name: SP_CSR0..SP_CSR1Access Type: Read/write • CPOL: Clock Polarity 0 = The inactive state value of SPCK

AT75C310116• SCBR: Serial Clock Baud RateIn master mode, the SPI interface uses a modulus counter to derive the SPCK baud rate from the SPI master clo

AT75C310117WD: Watchdog TimerThe AT75C310 has an internal watchdog timer which canbe used to prevent system lock-up if the software becomestrapped in

AT75C310118WD Overflow Mode RegisterName: WD_OMRAccess: Read/writeReset Value: 0 • WDEN: Watchdog Enable0 = Watchdog is disabled and does not generate

AT75C310119WD Clock Mode RegisterName: WD_CMRAccess: Read/writeReset Value: 0 • WDCLKS: Clock Selection • HPCV: High Preload Counter ValueCounter is p

AT75C31012AT75C310 Mode ControllerThe mode controller is a memory-mapped peripheral which sits on the APB. It is used to configure the mode in which t

AT75C310120WD Status RegisterName: WD_SRAccess: Read-only • WDOVF: Watchdog Overflow0 = No watchdog overflow.1 = A watchdog overflow has occurred sinc

AT75C310121WD Enabling SequenceTo enable the watchdog timer the sequence is as follows:1. Disable the watchdog by clearing the bit WDEN:Write 0x2340 t

AT75C310122Dual-port MailboxCommunication between the asynchronous ARM7TDMIand OakDSPCore are via the dual-port mailbox (DPMB). Itis assumed that each

AT75C310123Semaphore OperationThe DPMB supports semaphore registers to facilitate asyn-chronous communication between two processors. Eachof the eig

AT75C310124DPMB Register MapNote: 1. Base address is 0xFA000000 for OakA and 0xFB000000 for OakB.Table 23. ARM RegistersRegister Address(Offset from

AT75C310125DPMB Semaphore RegistersThe semaphore registers look the same from the ARM and the Oak sides. • Sem: Semaphore When low, the sender has rea

AT75C310126Assembly Source Code – Boot Program;-----------------------------------------------------------------------------;Cadence Design Systems Lt

AT75C310127B fiqvec ; FIQ;-----------------------------------------------------------------------------; Entry point.;--------------------------------

AT75C310128bl rx-poll-timedcmp r2, #Ox16bne remap;; A synch has been received look for the rest of the activation sequence;bl rx_poll_timedcmp r2, #Ox

AT75C310129eor r5, r5, r2mov r2, r2, LSL #8orr r4, r4, r2bl rx_polleor r5, r5, r2mov r2, r2, LSL #16orr r4, r4, r2bl rx_poll eor r5, r5, r2mov r2, r2,

AT75C31013• LP: Low Power ModeWhen high, the ARM is clocked at the low-power frequency. The DMC clock is disabled so the DRAM refresh is alsodisabled.

AT75C310130tst rl, #OxO1beq rx_poll_timedldr rl, USARTO_RHR_Regldr r2, [r1]mov pc, lr;----------------------------------------------------------------

AT75C310131DCD OxFF01800CUSARTO_CSR_RegDCD OxFF018014USARTO_RHR_RegDCD OxFF018018USARTO_THR_RegDCD OxFF01801CUSARTO_BR_RegDCD OxFF018020USARTO_ModC_Re

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

AT75C31014ID RegisterRegister Name: SIAP_ID• PKG: PackageThis bit reflects the state of the data bus width signal DBW and indicates the AT75C310 packa

AT75C31015EBI: External Bus InterfaceThe EBI generates the signals which control access to theexternal memory or peripheral devices. The EBI is fully

AT75C31016Signal InterfaceData Bus WidthA data bus width of 32 or 16 bits can be selected for eachchip select. This option is controlled by the DBW fi

AT75C31017Read ProtocolsThe SMC provides two alternative protocols for externalmemory read access: standard and early read. The differ-ence between th

AT75C31018• External WaitThe NWAIT input can be used to add wait states at anytime NWAIT is active low and is detected on the rising edgeof the clock.

AT75C31019SMC Chip Select RegisterRegister Name: SMC_CSR0..SMC_CSR3• DBW: Data Bus Width• WSE: Wait State Enable• NWS: Number of Wait StatesThis field

AT75C3102AT75C310 Pin ConfigurationTable 1. AT75C310 Pinout in 160-lead PQFP PackagePin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name1V

AT75C31020• PAGES: Page Size• TDF: Data Float Output Time• BAT: Byte Access Mode0 = Byte-write Mode1 = Byte-select Mode• CSEN: Chip Select EnableActiv

AT75C31021SMC Memory Control RegisterRegister Name: SMC_MCR• DRP: Data Read Protocol0 = Standard Read Mode1 = Early Read Mode31 30 29 28 27 26 25 24––

AT75C31022Switching WaveformsFigure 3 shows a write to memory 0, followed by a writeand a read to memory 1. SMC_CSR0 is programmed forone wait state w

AT75C31023Figure 4 shows a write and a read to memory 0, followedby a read and a write to memory 1. SMC_CSR0 is pro-grammed for zero wait states with

AT75C31024DMC: Dynamic Memory ControllerThe ARM can access external DRAM by means of theDRAM memory controller. The DMC sits on the ASB busand provide

AT75C31025DRAM Memory Region Configuration RegisterFor each of the two DRAM memory regions there is a memory-mapped register.Register Name: DMC_MR0..D

AT75C31026DRAM Common Configuration Register (DMC_CR)The Common Configuration Register defines parameters which are common to the two DRAM regions. Re

AT75C31027Dynamic Memory AccessesFigure 5 and Figure 6 describe the different bus operationsthat can be performed by DMC.Write Access Followed by Burs

AT75C31028Read and Write Accesses Followed by CAS before RAS RefreshFigure 6 shows a read access followed by a write. As theaccesses are to different

AT75C31029AIC: Advanced Interrupt Controller The AT75C310 has an eight-level priority, individuallymaskable interrupt controller. This feature substan

AT75C3103AT75C310 Pin DescriptionTable 2. AT75C310 Pin DescriptionBlock Pin Name Type FunctionCommon BusA[21:0] O Address BusD[15:0] I/O Data BusNREQ

AT75C31030Table 11. AIC Interrupt SourcesInterrupt Source Interrupt Name Interrupt Description0 FIQ/LOWPFast interrupt (external), low-power1 WDIRQWa

AT75C31031Priority ControllerThe NIRQ line is controlled by an eight-level priorityencoder. Each source has a programmable priority level of7 to 0. Le

AT75C31032code then checks the interrupt number and branches to the required service routine.6. The service routine should start by saving the Link Re

AT75C31033AIC User InterfaceBase Address: 0xFF030000 Note: 1. The reset value of this register depends on the level of the external IRQ lines. All oth

AT75C31034AIC Source Mode RegisterRegister Name: AIC_SMR0..AIC_SMR31Access Type: Read/writeReset Value: 0 • PRIOR: Priority LevelPrograms the prior

AT75C31035AIC FIQ Vector RegisterRegister Name: AIC_FVRAccess Type: Read-onlyReset Value: 0 • FIQV: FIQ Vector RegisterFIQ = 0x00000000 if FIQ activeF

AT75C31036AIC Interrupt Pending RegisterRegister Name: AIC_IPRAccess Type: Read-onlyReset Value: Undefined• Interrupt Pending0 = Corresponding interru

AT75C31037AIC Core Interrupt Status RegisterRegister Name: AIC_CISRAccess Type: Read-onlyReset Value: 0 • NFIQ: NFIQ Status 0 = NFIQ line inactive1 =

AT75C31038AIC Interrupt Disable Command RegisterRegister Name: AIC_IDCRAccess Type: Write-only • NFIQ: NFIQ Status 0 = NFIQ line inactive1 = NFIQ line

AT75C31039AIC Interrupt Set Command RegisterRegister Name: AIC_ISCRAccess Type: Write-only • NFIQ: NFIQ Status 0 = NFIQ line inactive1 = NFIQ line act

AT75C3104USART ARXDA I Receive DataTXDA O Transmit DataNRTSA O Ready to SendNCTSA I Clear To SendNDTRA O Data Terminal ReadyNDSRA/BOOTN I Data Set Rea

AT75C31040PIO: Parallel I/O ControllerThe AT75C310 has 23 programmable I/O lines. Three pinson the AT75C310 are dedicated as general-purpose I/Opins.

AT75C31041Figure 8. Parallel I/O Multiplexed with a Bi-directional SignalPadPIO_OSR1010PIO_PSRPIO_ODSR01PIO_PSREvent DetectionPIO_PDSRPIO_ISRPIO_IMRP

AT75C31042Note: 1. Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers.Note: 1. Bit number refe

AT75C31043PIO User InterfacePIO Controller A Base Address: 0xFF00C000PIO Controller B Base Address: 0xFF010000Notes: 1. The reset value of this regist

AT75C31044PIO Enable RegisterRegister Name: PIO_PERAccess Type: Write-only This register is used to enable individual pins to be controlled by the PIO

AT75C31045PIO Status RegisterRegister Name: PIO_PSRAccess Type: Read-onlyThis register indicates which pins are enabled for PIO control. This register

AT75C31046PIO Output Disable RegisterRegister Name: PIO_ODRAccess Type: Write-only This register is used to disable PIO output drivers. If the pin is

AT75C31047PIO Input Filter Enable RegisterRegister Name: PIO_IFERAccess Type: Write-only This register is used to enable input glitch filters. It affe

AT75C31048PIO Input Filter Status RegisterRegister Name: PIO_IFSRAccess Type: Read-onlyReset Value: 0 This register indicates which pins have glitch f

AT75C31049PIO Clear Output Data RegisterRegister Name: PIO_CODRAccess Type: Write-only This register is used to clear PIO output data. It affects the

AT75C3105Block DiagramFigure 1. AT75C310 Block DiagramIRQ ControllerSPITimer/Counter 0Timer/Counter 1Timer/Counter 2AMBATM BridgePeripheral DataContr

AT75C31050PIO Pin Data Status RegisterRegister Name: PIO_PDSRAccess Type: Read-onlyReset Value: UndefinedThis register shows the state of the physical

AT75C31051PIO Interrupt Disable RegisterRegister Name: PIO_IDRAccess Type: Write-only This register is used to disable PIO interrupts on the correspon

AT75C31052PIO Interrupt Status RegisterRegister Name: PIO_ISRAccess Type: Read-onlyReset Value: 0 This register indicates for each pin when a logic va

AT75C31053USART: Universal Synchronous/Asynchronous Receiver/TransmitterThe AT75C310 provides two identical, full-duplex, univer-sal synchronous/async

AT75C31054Pin DescriptionEach USART channel has the following external signals:Note: After a hardware reset, the USART pins are deselected by default

AT75C31055Notes: 1. CD = clock driver2. For information on obtaining exact baud rates using the value of CD given above, the selected clock frequency

AT75C31056ReceiverAsynchronous ReceiverThe USART is configured for asynchronous operationwhen SYNC = 0 (bit 7 of US_MR). In asynchronous mode,the USAR

AT75C31057Time-outThis function allows an idle condition on the RXD line to bedetected. The maximum delay for which the USART shouldwait for a new cha

AT75C31058Break A break condition is a low signal level which has a durationof at least one character (including start/stop bits and par-ity).Transmit

AT75C31059Interrupt GenerationEach status bit in US_CSR has a corresponding bit inUS_IER (Interrupt Enable) and US_IDR (Interrupt Disable)which contro

AT75C3106Architectural OverviewThe AT75C310 architecture consists of two main buses,the Advanced System Bus (ASB) and the AdvancedPeripheral Bus (APB)

AT75C31060Modem Control and Status SignalsNCTS: Clear to SendWhen low, this indicates that the modem or data set isready to exchange data. The NCTS si

AT75C31061USART User InterfaceBase Address USART A: 0xFF018000Base Address USART B: 0xFF01C000 Notes: 1. This may be 0x18 or 0x418 depending on the va

AT75C31062USART Control RegisterName: US_CRAccess Type: Write-only • RSTRX: Reset Receiver0 = No effect.1 = The receiver logic is reset.• RSTTX: Reset

AT75C31063USART Mode RegisterName: US_MRAccess Type: Read/write • USCLKS: Clock Selection (Baud Rate Generator Input Clock)• CHRL: Character LengthSta

AT75C31064• NBSTOP: Number of Stop BitsThe interpretation of the number of stop bits depends on SYNC. • CHMODE: Channel Mode • MODE9: 9-bit Character

AT75C31065USART Interrupt Enable RegisterName: US_IERAccess Type: Write-only• RXRDY: Enable RXRDY Interrupt0 = No effect.1 = Enables RXRDY Interrupt.•

AT75C31066USART Interrupt Disable RegisterName: US_IDRAccess Type: Write-only • RXRDY: Disable RXRDY Interrupt0 = No effect.1 = Disables RXRDY Interru

AT75C31067USART Interrupt Mask RegisterName: US_IMRAccess Type: Read-only• RXRDY: RXRDY Interrupt Mask0 = RXRDY Interrupt is disabled.1 = RXRDY Interr

AT75C31068USART Channel Status RegisterName: US_CSRAccess Type: Read-only • RXRDY: Receiver Ready0 = No complete character has been received since the

AT75C31069• TXEMPTY: Transmitter Empty0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted.1 = The

AT75C3107Memory MapThe memory map is divided into memory regions of 64megabytes. The top seven memory regions are reservedand subdivided for internal

AT75C31070USART Receiver Holding RegisterName: US_RHRAccess Type: Read-only • RXCHR: Received CharacterLast character received if RXRDY is set. When n

AT75C31071USART Baud Rate Generator RegisterName: US_BRGRAccess Type: Read/write • CD: Clock DivisorThis register has no effect if synchronous mode is

AT75C31072USART Receiver Time-out RegisterName: US_RTORAccess Type: Read/write • TO: Time-out ValueWhen a value is written to this register, a Start T

AT75C31073USART Transmitter Time-guard RegisterName: US_TTGRAccess Type: Read/write • TG: Time-guard Value Time-guard duration = TG x Bit periodUSART

AT75C31074USART Receive Counter RegisterName: US_RCRAccess Type: Read/write• RXCTR: Receive CounterRXCTR must be loaded with the size of the receive b

AT75C31075USART Transmit Counter RegisterName: US_TCRAccess Type: Read/write • TXCTR: Transmit CounterTXCTR must be loaded with the size of the transm

AT75C31076Modem Control Register Register Name: US_MC This register controls the interface with the modem or data set (or a peripheral device emulatin

AT75C31077Modem Status Register Register Name: US_MS This register provides the current state of the control lines from the modem (or peripheral devic

AT75C31078TC: Timer/Counter The AT75C310 features a timer/counter block whichincludes three identical 16-bit timer/counter channels. Eachchannel can b

AT75C31079Signal Name DescriptionNote: After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configu

AT75C3108Peripheral Memory MapThe register maps for each peripheral are described in the corresponding sections of this datasheet. The peripheral mem-

AT75C31080Figure 17. Clock SelectionClock ControlThe clock of each counter can be controlled in two differentways: it can be enabled/disabled and sta

AT75C31081Capture Mode Capture mode is entered by clearing the WAVE parameterin TC_CMR (Channel Mode Register). Capture modeallows the TC channel to p

AT75C31082Figure 19. Capture ModeACLK/2ACLK/8ACLK/32ACLK/128ACLK/1024XC0XC1XC2TCCLKSCLKIQSRSRQCLKSTA CLKEN CLKDISBURSTTIOBRegister CCapture Register

AT75C31083Waveform ModeWaveform mode is entered by setting the WAVE parameterin TC_CMR (Channel Mode Register). Waveform mode allows the TC channel to

AT75C31084Figure 20. Waveform Mode ACLK/2ACLK/8ACLK/32ACLK/128ACLK/1024XC0XC1XC2TCCLKSCLKIQSRSRQCLKSTA CLKEN CLKDISCPCDISBURSTTIOBRegister A Register

AT75C31085TC User InterfaceTC Base Address: 0xFF014000TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC channe

AT75C31086TC Block Control Register Register Name: TC_BCRAccess Type: Write-only• SYNC: Synchro Command0 = No effect.1 = Asserts the SYNC signal which

AT75C31087TC Block Mode Register Register Name: TC_BMRAccess Type: Read/write • TC0XC0S: External Clock Signal 0 Selection • TC1XC1S: External Clock S

AT75C31088TC Channel Control Register Register Name: TC_CCRAccess Type: Write-only • CLKEN: Counter Clock Enable Command0 = No effect.1 = Enables the

AT75C31089TC Channel Mode Register: Capture ModeRegister Name: TC_CMRAccess Type: Read/write • TCCLKS: Clock Selection • CLKI: Clock Invert 0 = Counte

AT75C3109InitializationReset initializes the user interface registers to their defaultstates as defined in the peripheral sections of thisdatasheet an

AT75C31090• ETRGEDG: External Trigger Edge Selection• ABETRG: TIOA or TIOB External Trigger Selection0 = TIOB is used as an external trigger.1 = TIOA

AT75C31091TC Channel Mode Register: Waveform ModeRegister Name: TC_CMRAccess Type: Read/write • TCCLKS: Clock Selection• CLKI: Clock Invert 0 = Counte

AT75C31092• EEVTEDG: External Event Edge Selection• EEVT: External Event Selection Note: 1. If TIOB is chosen as the external event signal, it is conf

AT75C31093• AEEVT: External Event Effect on TIOA• ASWTRG: Software Trigger Effect on TIOA • BCPB: RB Compare Effect on TIOB • BCPC: RC Compare Effect

AT75C31094• BSWTRG: Software Trigger Effect on TIOBBSWTRG Effect00None01Set1 0 Clear1 1 Toggle

AT75C31095TC Counter Value Register Register Name: TC_CVRAccess Type: Read-only • CV: Counter ValueCV contains the counter value in real-time.TC Regis

AT75C31096TC Register BRegister Name: TC_RBAccess Type: Read-only if WAVE = 0, Read/write if WAVE = 1 • RB: Register BRB contains the Register B value

AT75C31097TC Status Register Register Name: TC_SRAccess Type: Read/write • COVFS: Counter Overflow Status0 = No counter overflow has occurred since th

AT75C31098TC Interrupt Enable Register Register Name: TC_IERAccess Type: Write-only • COVFS: Counter Overflow 0 = No effect.1 = Enables the Counter Ov

AT75C31099TC Interrupt Disable Register Register Name: TC_IDRAccess Type: Write-only • COVFS: Counter Overflow 0 = No effect.1 = Disables the Counter