Rainbow-electronics MAX9218 Instrukcja Użytkownika Pobierz pdf (Strona 10)

MAX9218

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Deserializer

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Detailed Description

The MAX9218 DC-balanced deserializer operates at a

parallel clock frequency of 3MHz to 35MHz, deserializ-

ing video data to the RGB_OUT[17:0] outputs when the

data enable output DE_OUT is high, or control data to

the CNTL_OUT[8:0] outputs when DE_OUT is low. The

video phase words are decoded using 2 overhead bits,

EN0 and EN1. Control phase words are decoded with 1

overhead bit, EN0. Encoding, performed by the

MAX9217 serializer, reduces EMI and maintains DC

balance across the serial cable. The serial input word

formats are shown in Table 1 and Table 2.

Control data inputs C0 to C4, each repeated over 3 seri-

al bit times by the serializer, are decoded using majority

voting. Two or three bits at the same state determine the

state of the recovered bit, providing single bit-error tol-

erance for C0 to C4. The state of C5 to C8 is deter-

mined by the level of the bit itself (no voting is used).

AC-Coupling Benefits

AC-coupling increases the input voltage of the LVDS

receiver to the voltage rating of the capacitor. Two

capacitors are sufficient for isolation, but four capaci-

tors—two at the serializer output and two at the deseri-

alizer input—provide protection if either end of the

cable is shorted to a high voltage. AC-coupling blocks

low-frequency ground shifts and common-mode noise.

The MAX9217 serializer can also be DC-coupled to the

MAX9218 deserializer. Figure 10 is the AC-coupled

serializer and deserializer with two capacitors per link,

and Figure 11 is the AC-coupled serializer and deseri-

alizer with four capacitors per link.

Applications Information

Selection of AC-Coupling Capacitors

See Figure 12 for calculating the capacitor values for

AC-coupling, depending on the parallel clock frequen-

cy. The plot shows capacitor values for two- and four-

capacitor-per-link systems. For applications using less

than 18MHz clock frequency, use 0.125µF capacitors.

Termination and Input Bias

The IN+ and IN- LVDS inputs are internally connected

to +1.2V through 35kΩ (min) to provide biasing for AC-

coupling (Figure 1). Assuming 100Ω interconnect, the

LVDS input can be terminated with a 100Ω resistor.

Match the termination to the differential impedance of

the interconnect.

Use a Thevenin termination, providing 1.2V bias, on an

AC-coupled link in noisy environments. For intercon-

nect with 100Ω differential impedance, pull each LVDS

line up to V

with 130Ω and down to ground with 82Ω

at the deserializer input (Figure 10 and Figure 11). This

termination provides both differential and common-

mode termination. The impedance of the Thevenin ter-

mination should be half the differential impedance of

the interconnect and provide a bias voltage of 1.2V.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17

Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.

Table 1. Serial Video Phase Word Format

012345678910111213141516171819

E N 0C0C0C0C1C1C1C2C2C2C3C3C3C4C4C4C5C6C7C8

Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.

Table 2. Serial Control Phase Word Format

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 16

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