
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
_______________________________________________________________________________________ 9
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
t
PLLREF
TRANSITION
WORD
FOUND
RECOVERED CLOCK
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
t
PDD
0.8V
2.0V
OUTEN
ACTIVEHIGH-Z
LOCK
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
t
OE
0.8V
Figure 7. PLL Lock to REFCLK and Power-Down Delay
Figure 8. Output Enable Time
OUTEN
HIGH-ZACTIVE
LOCK
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
t
OZ
2.0V
Figure 9. Output Disable Time
Komentarze do niniejszej Instrukcji