Rainbow-electronics W90P710CDG Instrukcja Użytkownika Pobierz pdf (Strona 41)

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W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 41 - Revision B2

Table6.2.6 Half-word access read operation with Big Endian

ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)

XD WIDTH WORD HALF WORD BYTE

Bit Number

CPU Reg Data

15 0

HAL HAU HA HA

Bit Number

15 0

Bit Number

15 0

HAL HAL HA HA HA+1

SDQM [3-0]

AAUU UUAA XXAA XXXA XXXA

Bit Number

31 0

AB CD

31 0

AB CD

15 0

7 0

Bit Number

Ext. Mem Data

31 0

ABCD

15 0

7 0

Timing Sequence 1st read 2nd read

Table 6.2.7 and Table 6.2.8

Using big-endian and byte access, Program/Data path between register and external memory.

BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F

BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D

BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 551 552

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