Rainbow-electronics ATmega128L Instrukcja Użytkownika Pobierz pdf (Strona 249)

249

ATmega128(L)

2467B–09/01

Figure 124. General Port Pin Schematic diagram

Boundary-scan and the Two-

wire Interface

The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the

scan-chain; Two-wire Interface Enable – TWIEN. As shown in

Figure 125, the TWIEN

signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital

port pins. A general scan cell as shown in

Figure 129 is attached to the TWIEN signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordi-

nary scan support for digital port pins suffice for connectivity tests. The only reason

for having TWIEN in the scan path, is to be able to disconnect the slew-rate control

buffer when doing boundary-scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will

lead to drive contention.

CLK

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

See Boundary-Scan description

for details!

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin Pxn

OCxn: OUTPUT CONTROL for pin Pxn

ODxn: OUTPUT DATA to pin Pxn

IDxn: INPUT DATA from pin Pxn

1 2 ... 244 245 246 247 248 249 250 251 252 253 254 ... 330 331

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