
ATmega163(L)
108
Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1)
Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5)
0
1
TWEN
SCL/SDA in
SCL/SDA out
PCn
DDCn
n
n = 0, 1
PUD
0
1
PUD: PULL-UP DISABLE
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PCn
R
R
WP:
WD:
RL:
RP:
RD:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
DDCn
PORTCn
RL
RP
PUD
PUD: PULL-UP DISABLE
n: 2..5
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