Rainbow-electronics ATmega3290P_V Instrukcja Użytkownika

2552H–AVR–11/06Features• High Performance, Low Power AVR® 8-Bit Microcontroller• Advanced RISC Architecture– 130 Powerful Instructions – Most Single

10ATmega329/3290/649/64902552H–AVR–11/06the operation is executed, and the result is stored back in the Register File – in oneclock cycle.Six of the 3

100ATmega329/3290/649/64902552H–AVR–11/06Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-initions. However, the

101ATmega329/3290/649/64902552H–AVR–11/06Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,the compare match is ign

102ATmega329/3290/649/64902552H–AVR–11/06OCR0A – Output Compare Register AThe Output Compare Register A contains an 8-bit value that is continuously c

103ATmega329/3290/649/64902552H–AVR–11/06Timer/Counter0 and Timer/Counter1 PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module

104ATmega329/3290/649/64902552H–AVR–11/06the edge detector uses sampling, the maximum frequency of an external clock it candetect is half the sampling

105ATmega329/3290/649/64902552H–AVR–11/0616-bit Timer/Counter1The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agemen

106ATmega329/3290/649/64902552H–AVR–11/06Figure 41. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 29 on page 68, a

107ATmega329/3290/649/64902552H–AVR–11/06also set the Compare Match Flag (OCF1A/B) which can be used to generate an OutputCompare interrupt request.Th

108ATmega329/3290/649/64902552H–AVR–11/06Accessing 16-bit RegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCP

109ATmega329/3290/649/64902552H–AVR–11/06The following code examples show how to do an atomic read of the TCNT1 Registercontents. Reading any of the O

11ATmega329/3290/649/64902552H–AVR–11/06AVR Status Register The Status Register contains information about the result of the most recently executedari

110ATmega329/3290/649/64902552H–AVR–11/06The following code examples show how to do an atomic write of the TCNT1 Registercontents. Writing any of the

111ATmega329/3290/649/64902552H–AVR–11/06Timer/Counter Clock SourcesThe Timer/Counter can be clocked by an internal or an external clock source. The c

112ATmega329/3290/649/64902552H–AVR–11/06how waveforms are generated on the Output Compare outputs OC1x. For more detailsabout advanced counting seque

113ATmega329/3290/649/64902552H–AVR–11/06The ICR1 Register can only be written when using a Waveform Generation mode thatutilizes the ICR1 Register fo

114ATmega329/3290/649/64902552H–AVR–11/06Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis-ter (OCR

115ATmega329/3290/649/64902552H–AVR–11/06(Buffer or Compare) Register is only changed by a write operation (the Timer/Counterdoes not update this regi

116ATmega329/3290/649/64902552H–AVR–11/06Compare Match Output UnitThe Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener-ator

117ATmega329/3290/649/64902552H–AVR–11/06Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM1x1:0 bits differently in norma

118ATmega329/3290/649/64902552H–AVR–11/06Figure 46. CTC Mode, Timing DiagramAn interrupt can be generated at each time the counter value reaches the

119ATmega329/3290/649/64902552H–AVR–11/06The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by eitherICR1 or OCR1A. The min

12ATmega329/3290/649/64902552H–AVR–11/06General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In orde

120ATmega329/3290/649/64902552H–AVR–11/06double buffered. This feature allows the OCR1A I/O location to be written anytime.When the OCR1A I/O location

121ATmega329/3290/649/64902552H–AVR–11/06OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set toMAX). The PWM resolution in b

122ATmega329/3290/649/64902552H–AVR–11/06ing slope is determined by the previous TOP value, while the length of the rising slope isdetermined by the n

123ATmega329/3290/649/64902552H–AVR–11/06In phase and frequency correct PWM mode the counter is incremented until the countervalue matches either the

124ATmega329/3290/649/64902552H–AVR–11/06non-inverted PWM and an inverted PWM output can be generated by setting theCOM1x1:0 to three (See Table 1 on

125ATmega329/3290/649/64902552H–AVR–11/06Figure 51. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)Figure 52 shows the co

126ATmega329/3290/649/64902552H–AVR–11/06Figure 53. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)16-bit Timer/Counter Register Descriptio

127ATmega329/3290/649/64902552H–AVR–11/06Table 62 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thefast PWM mode.Note: 1. A sp

128ATmega329/3290/649/64902552H–AVR–11/06Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the fu

129ATmega329/3290/649/64902552H–AVR–11/06(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.When the ICR1 i

13ATmega329/3290/649/64902552H–AVR–11/06The X-register, Y-register, and Z-registerThe registers R26..R31 have some added functions to their general pu

130ATmega329/3290/649/64902552H–AVR–11/06TCNT1H and TCNT1L – Timer/Counter1The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) giv

131ATmega329/3290/649/64902552H–AVR–11/06TIMSK1 – Timer/Counter1 Interrupt Mask Register• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enabl

132ATmega329/3290/649/64902552H–AVR–11/06• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match FlagThis flag is set in the timer clock cycle after t

133ATmega329/3290/649/64902552H–AVR–11/068-bit Timer/Counter2 with PWM and Asynchronous OperationTimer/Counter2 is a general purpose, single compare u

134ATmega329/3290/649/64902552H–AVR–11/06ment) its value. The Timer/Counter is inactive when no clock source is selected. Theoutput from the Clock Sel

135ATmega329/3290/649/64902552H–AVR–11/06top Signalizes that TCNT2 has reached maximum value.bottom Signalizes that TCNT2 has reached minimum value (z

136ATmega329/3290/649/64902552H–AVR–11/06The OCR2A Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the Normal

137ATmega329/3290/649/64902552H–AVR–11/06Compare Match Output UnitThe Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener-ator

138ATmega329/3290/649/64902552H–AVR–11/06Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins,

139ATmega329/3290/649/64902552H–AVR–11/06compare match. The counter will then have to count to its maximum value (0xFF) andwrap around starting at 0x0

14ATmega329/3290/649/64902552H–AVR–11/06Instruction Execution TimingThis section describes the general access timing concepts for instruction executio

140ATmega329/3290/649/64902552H–AVR–11/06The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. Ifthe interrupt is enabled,

141ATmega329/3290/649/64902552H–AVR–11/06Figure 60. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV2) is set each time the

142ATmega329/3290/649/64902552H–AVR–11/06• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare

143ATmega329/3290/649/64902552H–AVR–11/06Figure 63. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)Figure 64 shows the se

144ATmega329/3290/649/64902552H–AVR–11/068-bit Timer/Counter Register DescriptionTCCR2A – Timer/Counter Control Register A• Bit 7 – FOC2A: Force Outpu

145ATmega329/3290/649/64902552H–AVR–11/06• Bit 5:4 – COM2A1:0: Compare Match Output Mode AThese bits control the Output Compare pin (OC2A) behavior. I

146ATmega329/3290/649/64902552H–AVR–11/06The three Clock Select bits select the clock source to be used by the Timer/Counter, seeTable 71.TCNT2 – Time

147ATmega329/3290/649/64902552H–AVR–11/06Asynchronous operation of the Timer/CounterASSR – Asynchronous Status Register• Bit 4 – EXCLK: Enable Externa

148ATmega329/3290/649/64902552H–AVR–11/06Asynchronous Operation of Timer/Counter2When Timer/Counter2 operates asynchronously, some considerations must

149ATmega329/3290/649/64902552H–AVR–11/06• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously

15ATmega329/3290/649/64902552H–AVR–11/06moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see“Boot Loader Support – Read-W

150ATmega329/3290/649/64902552H–AVR–11/06(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), theTimer/Counter2 Compare match Int

151ATmega329/3290/649/64902552H–AVR–11/06GTCCR – General Timer/Counter Control Register• Bit 1 – PSR2: Prescaler Reset Timer/Counter2When this bit is

152ATmega329/3290/649/64902552H–AVR–11/06SPI – Serial Peripheral InterfaceThe ATmega329/3290/649/6490 SPI includes the following features:•Full-duplex

153ATmega329/339/649/6592552H–AVR–11/06change data. Data is always shifted from Master to Slave on the Master Out – Slave In,MOSI, line, and from Slav

154ATmega329/339/649/6592552H–AVR–11/06When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins isoverridden according to Table

155ATmega329/339/649/6592552H–AVR–11/06Note: 1. See “About Code Examples” on page 8.SPI_MasterInit:; Set MOSI and SCK output, all others inputldi r17,

156ATmega329/339/649/6592552H–AVR–11/06The following code examples show how to initialize the SPI as a Slave and how to per-form a simple reception.No

157ATmega329/339/649/6592552H–AVR–11/06SS Pin FunctionalitySlave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input

158ATmega329/339/649/6592552H–AVR–11/06be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR tore-enable SPI Master mode.•

159ATmega329/339/649/6592552H–AVR–11/06SPSR – SPI Status Register• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF Flag i

16ATmega329/3290/649/64902552H–AVR–11/06When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any

160ATmega329/339/649/6592552H–AVR–11/06Data Modes There are four combinations of SCK phase and polarity with respect to serial data,which are determin

161ATmega329/3290/649/64902552H–AVR–11/06USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible

162ATmega329/3290/649/64902552H–AVR–11/06The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock

163ATmega329/3290/649/64902552H–AVR–11/06Figure 71. Clock Generation Logic, Block DiagramSignal description:txclk Transmitter clock (Internal Signal)

164ATmega329/3290/649/64902552H–AVR–11/06Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)BAUD Baud rate (in bits per

165ATmega329/3290/649/64902552H–AVR–11/06Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as eitherclo

166ATmega329/3290/649/64902552H–AVR–11/06Sp Stop bit, always high.IDLE No transfers on the communication line (RxD or TxD). An IDLE line must behigh.T

167ATmega329/3290/649/64902552H–AVR–11/06Note: 1. See “About Code Examples” on page 8.More advanced initialization routines can be made that include f

168ATmega329/3290/649/64902552H–AVR–11/06Data Transmission – The USART TransmitterThe USART Transmitter is enabled by setting the Transmit Enable (TXE

169ATmega329/3290/649/64902552H–AVR–11/06Sending Frames with 9 Data BitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the T

17ATmega329/3290/649/64902552H–AVR–11/06AVR ATmega329/3290/649/6490 MemoriesThis section describes the different memories in the ATmega329/3290/649/64

170ATmega329/3290/649/64902552H–AVR–11/06Transmitter Flags and InterruptsThe USART Transmitter has two flags that indicate its state: USART Data Regis

171ATmega329/3290/649/64902552H–AVR–11/06Data Reception – The USART ReceiverThe USART Receiver is enabled by writing the Receive Enable (RXENn) bit in

172ATmega329/3290/649/64902552H–AVR–11/06The following code example shows a simple USART receive function that handles bothnine bit characters and the

173ATmega329/3290/649/64902552H–AVR–11/06Receive Compete Flag and InterruptThe USART Receiver has one flag that indicates the Receiver state.The Recei

174ATmega329/3290/649/64902552H–AVR–11/06Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

175ATmega329/3290/649/64902552H–AVR–11/06Figure 74. Start Bit SamplingWhen the clock recovery logic detects a high (idle) to low (start) transition o

176ATmega329/3290/649/64902552H–AVR–11/06Figure 76. Stop Bit Sampling and Next Start Bit SamplingThe same majority voting is done to the stop bit as

177ATmega329/3290/649/64902552H–AVR–11/06The recommendations of the maximum receiver baud rate error was made under theassumption that the Receiver an

178ATmega329/3290/649/64902552H–AVR–11/06Multi-processor Communication ModeSetting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enable

179ATmega329/3290/649/64902552H–AVR–11/06USART Register DescriptionUDRn – USART I/O Data Register nThe USART Transmit Data Buffer Register and USART R

18ATmega329/3290/649/64902552H–AVR–11/06SRAM Data Memory Figure 10 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.The ATmega329/3290/6

180ATmega329/3290/649/64902552H–AVR–11/06• Bit 4 – FEn: Frame ErrorThis bit is set if the next character in the receive buffer had a Frame Error whenr

181ATmega329/3290/649/64902552H–AVR–11/06• Bit 3 – TXENn: Transmitter EnableWriting this bit to one enables the USART Transmitter. The Transmitter wil

182ATmega329/3290/649/64902552H–AVR–11/06• Bit 3 – USBSn: Stop Bit SelectThis bit selects the number of stop bits to be inserted by the Transmitter. T

183ATmega329/3290/649/64902552H–AVR–11/06• Bit 15:12 – Reserved BitsThese bits are reserved for future use. For compatibility with future devices, the

184ATmega329/3290/649/64902552H–AVR–11/06Table 86. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc

185ATmega329/3290/649/64902552H–AVR–11/06Table 87. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc

186ATmega329/3290/649/64902552H–AVR–11/06Table 88. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc

187ATmega329/3290/649/64902552H–AVR–11/06USI – Universal Serial InterfaceThe Universal Serial Interface, or USI, provides the basic hardware resources

188ATmega329/3290/649/64902552H–AVR–11/06selected from three different sources: The USCK pin, Timer/Counter0 Compare Matchor from software.The Two-wir

189ATmega329/3290/649/64902552H–AVR–11/06Figure 79. Three-wire Mode, Timing DiagramThe Three-wire mode timing is shown in Figure 79. At the top of th

19ATmega329/3290/649/64902552H–AVR–11/06Figure 11. On-chip Data SRAM Access CyclesEEPROM Data Memory The ATmega329/3290/649/6490 contains 1/2K bytes

190ATmega329/3290/649/64902552H–AVR–11/06SPI Master Operation ExampleThe following code demonstrates how to use the USI module as a SPI Master:SPITran

191ATmega329/3290/649/64902552H–AVR–11/06The following code demonstrates how to use the USI module as a SPI Master with max-imum speed (fsck = fck/4):

192ATmega329/3290/649/64902552H–AVR–11/06ferred to the master device, and when the transfer is completed the data received fromthe Master is stored ba

193ATmega329/3290/649/64902552H–AVR–11/06Figure 81. Two-wire Mode, Typical Timing DiagramReferring to the timing diagram (Figure 81.), a bus transfer

194ATmega329/3290/649/64902552H–AVR–11/06Start Condition Detector The start condition detector is shown in Figure 82. The SDA line is delayed (in the

195ATmega329/3290/649/64902552H–AVR–11/06USI Register DescriptionsUSIDR – USI Data RegisterThe USI uses no buffering of the Serial Register, i.e., whe

196ATmega329/3290/649/64902552H–AVR–11/06When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition isdetected. The flag is cle

197ATmega329/3290/649/64902552H–AVR–11/06USICR – USI Control RegisterThe Control Register includes interrupt enable control, wire mode setting, Clock

198ATmega329/3290/649/64902552H–AVR–11/06Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)respectively to avoid co

199ATmega329/3290/649/64902552H–AVR–11/06• Bit 3..2 – USICS1..0: Clock Source SelectThese bits set the clock source for the Shift Register and counter

2ATmega329/3290/649/64902552H–AVR–11/06Features (Continued)• Ultra-Low Power Consumption– Active Mode: 1 MHz, 1.8V: 350 µA32 kHz, 1.8V: 20 µA (includi

20ATmega329/3290/649/64902552H–AVR–11/06EEARH and EEARL – The EEPROM Address Register• Bits 15:11 – Res: Reserved BitsThese bits are reserved bits in

200ATmega329/3290/649/64902552H–AVR–11/06Analog ComparatorOverview The Analog Comparator compares the input values on the positive pin AIN0 and nega-t

201ATmega329/3290/649/64902552H–AVR–11/06• Bit 7 – ACD: Analog Comparator DisableWhen this bit is written logic one, the power to the Analog Comparato

202ATmega329/3290/649/64902552H–AVR–11/06Analog Comparator Multiplexed InputIt is possible to select any of the ADC7..0 pins to replace the negative i

203ATmega329/3290/649/64902552H–AVR–11/06Analog to Digital ConverterFeatures • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ± 2 LSB Absolute Acc

204ATmega329/3290/649/64902552H–AVR–11/06Figure 84. Analog to Digital Converter Block SchematicOperation The ADC converts an analog input voltage to

205ATmega329/3290/649/64902552H–AVR–11/06to Data Registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is

206ATmega329/3290/649/64902552H–AVR–11/06The ADSC bit will be read as one during a conversion, independently of how the conver-sion was started.Presca

207ATmega329/3290/649/64902552H–AVR–11/06In Free Running mode, a new conversion will be started immediately after the conver-sion completes, while ADS

208ATmega329/3290/649/64902552H–AVR–11/06Figure 90. ADC Timing Diagram, Free Running ConversionChanging Channel or Reference SelectionThe MUXn and RE

209ATmega329/3290/649/64902552H–AVR–11/06ADC Input Channels When changing channel selections, the user should observe the following guidelines toensur

21ATmega329/3290/649/64902552H–AVR–11/06Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. Whenad

210ATmega329/3290/649/64902552H–AVR–11/06Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 91. An a

211ATmega329/3290/649/64902552H–AVR–11/06Figure 92. ADC Power ConnectionsADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linear

212ATmega329/3290/649/64902552H–AVR–11/06• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x

213ATmega329/3290/649/64902552H–AVR–11/06• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two

214ATmega329/3290/649/64902552H–AVR–11/06Figure 97. Differential Measurement RangeADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result) Vo

215ATmega329/3290/649/64902552H–AVR–11/06ADMUX – ADC Multiplexer Selection Register• Bit 7:6 – REFS1:0: Reference Selection BitsThese bits select the

216ATmega329/3290/649/64902552H–AVR–11/06Table 96. Input Channel SelectionsMUX4..0 Single Ended Input Positive Differential Input Negative Differenti

217ATmega329/3290/649/64902552H–AVR–11/06ADCSRA – ADC Control and Status Register A• Bit 7 – ADEN: ADC EnableWriting this bit to one enables the ADC.

218ATmega329/3290/649/64902552H–AVR–11/06ADCL and ADCH – The ADC Data RegisterADLAR = 0ADLAR = 1When an ADC conversion is complete, the result is foun

219ATmega329/3290/649/64902552H–AVR–11/06DIDR0 – Digital Input Disable Register 0• Bit 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input DisableWhen this bit is

22ATmega329/3290/649/64902552H–AVR–11/06The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume

220ATmega329/3290/649/64902552H–AVR–11/06LCD Controller The LCD Controller/driver is intended for monochrome passive liquid crystal display(LCD) with

221ATmega329/3290/649/64902552H–AVR–11/06Figure 98. LCD Module Block Diagram LCD Clock Sources The LCD Controller can be clocked by an internal synch

222ATmega329/3290/649/64902552H–AVR–11/06Addressing COM0 starts a frame by driving opposite phase with large amplitude out onCOM0 compared to none add

223ATmega329/3290/649/64902552H–AVR–11/06Mode of OperationStatic Duty and Bias If all segments on a LCD have one electrode common, then each segment m

224ATmega329/3290/649/64902552H–AVR–11/061/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty).Waveform

225ATmega329/3290/649/64902552H–AVR–11/06Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can beselected

226ATmega329/3290/649/64902552H–AVR–11/06LCD Usage The following section describes how to use the LCD.LCD Initialization Prior to enabling the LCD som

227ATmega329/3290/649/64902552H–AVR–11/06Note: 1. See “About Code Examples” on page 8.Assembly Code Example(1)LCD_Init:; Use 32 kHz crystal oscillator

228ATmega329/3290/649/64902552H–AVR–11/06Before a re-initialization is done, the LCD controller/driver should be disabledUpdating the LCD Display memo

229ATmega329/3290/649/64902552H–AVR–11/06Note: 1. See “About Code Examples” on page 8.Assembly Code Example(1)LCD_disable:; Wait until a new frame is

23ATmega329/3290/649/64902552H–AVR–11/06EEPROM Write During Power-down Sleep ModeWhen entering Power-down sleep mode while an EEPROM write operation i

230ATmega329/3290/649/64902552H–AVR–11/06LCDCRA – LCD Control and Status Register A• Bit 7 – LCDEN: LCD EnableWriting this bit to one enables the LCD

231ATmega329/3290/649/64902552H–AVR–11/06either Timer/Counter Oscillator or external clock, depending on EXCLK in ASSR. See“Asynchronous operation of

232ATmega329/3290/649/64902552H–AVR–11/06LCDFRR – LCD Frame Rate Register• Bit 7 – Res: Reserved BitThis bit is reserved bit in the ATmega329/3290/649

233ATmega329/3290/649/64902552H–AVR–11/06The frame frequency can be calculated by the following equation:Where:N = prescaler divider (16, 64, 128, 256

234ATmega329/3290/649/64902552H–AVR–11/06LCDCCR – LCD Contrast Control Register• Bits 7:5 – LCDDC2:0: LDC Display ConfigurationThe LCDDC2:0 bits deter

235ATmega329/3290/649/64902552H–AVR–11/06LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visi-ble).

236ATmega329/3290/649/64902552H–AVR–11/06JTAG Interface and On-chip Debug SystemFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan

237ATmega329/3290/649/64902552H–AVR–11/06The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the

238ATmega329/3290/649/64902552H–AVR–11/06Figure 107. TAP Controller State DiagramTAP Controller The TAP controller is a 16-state finite state machine

239ATmega329/3290/649/64902552H–AVR–11/06state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.• At the TMS

24ATmega329/3290/649/64902552H–AVR–11/06level of the internal BOD does not match the needed detection level, an external lowVCC reset Protection circu

240ATmega329/3290/649/64902552H–AVR–11/06A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Spe-cific JTAG Instructions

241ATmega329/3290/649/64902552H–AVR–11/06On-chip Debug Related Register in I/O MemoryOCDR – On-chip Debug RegisterThe OCDR Register provides a communi

242ATmega329/3290/649/64902552H–AVR–11/06IEEE 1149.1 (JTAG) Boundary-scanFeatures • JTAG (IEEE std. 1149.1 compliant) Interface• Boundary-scan Capabil

243ATmega329/3290/649/64902552H–AVR–11/06Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-ter is s

244ATmega329/3290/649/64902552H–AVR–11/06Figure 109. Reset RegisterBoundary-scan Chain The Boundary-scan Chain has the capability of driving and obse

245ATmega329/3290/649/64902552H–AVR–11/06SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot ofth

246ATmega329/3290/649/64902552H–AVR–11/06MCUSR – MCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCUre

247ATmega329/3290/649/64902552H–AVR–11/06Figure 110. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.DQ DQG0101DQ DQG01010101DQ

248ATmega329/3290/649/64902552H–AVR–11/06Figure 111. General Port Pin Schematic DiagramScanning the RESET Pin The RESET pin accepts 5V active low log

249ATmega329/3290/649/64902552H–AVR–11/06Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RCOs

25ATmega329/3290/649/64902552H–AVR–11/06System Clock and Clock OptionsClock Systems and their DistributionFigure 12 presents the principal clock syste

250ATmega329/3290/649/64902552H–AVR–11/06Scanning the Analog ComparatorThe relevant Comparator signals regarding Boundary-scan are shown in Figure 114

251ATmega329/3290/649/64902552H–AVR–11/06Scanning the ADC Figure 116 shows a block diagram of the ADC with all relevant control and observe sig-nals.

252ATmega329/3290/649/64902552H–AVR–11/06Table 111. Boundary-scan Signals for the ADC(1)Signal NameDirection as seenfrom the ADC DescriptionRecommend

253ATmega329/3290/649/64902552H–AVR–11/06Note: 1. Incorrect setting of the switches in Figure 116 will make signal contention and may damage the part.

254ATmega329/3290/649/64902552H–AVR–11/06As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3when the power supply

255ATmega329/3290/649/64902552H–AVR–11/06ATmega329/3290/649/6490 Boundary-scan OrderTable 113 and Table 114 shows the Scan order between TDI and TDO w

256ATmega329/3290/649/64902552H–AVR–11/06169 MUXEN_4168 MUXEN_3167 MUXEN_2166 MUXEN_1165 MUXEN_0164 NEGSEL_2163 NEGSEL_1162 NEGSEL_0161 PASSEN160 PREC

257ATmega329/3290/649/64902552H–AVR–11/06133 PB0.Data Port B132 PB0.Control131 PB0.Pull-up_Enable130 PB1.Data129 PB1.Control128 PB1.Pull-up_Enable127

258ATmega329/3290/649/64902552H–AVR–11/06100 EXTCLKEN Enable signals for main Clock/Oscillators99 OSCON98 RCOSCEN97 OSC32EN96 EXTCLK (XTAL1) Clock inp

259ATmega329/3290/649/64902552H–AVR–11/0664 PG1.Control63 PG1.Pull-up_Enable62 PC0.Data Port C61 PC0.Control60 PC0.Pull-up_Enable59 PC1.Data58 PC1.Con

26ATmega329/3290/649/64902552H–AVR–11/06ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks

260ATmega329/3290/649/64902552H–AVR–11/06Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.28 PA5.Control27 PA5.Pull-up_Enable26 PA4.Data25

261ATmega329/3290/649/64902552H–AVR–11/06Table 114. ATmega3290/6490 Boundary-scan Order, 100-pinBit Number Signal Name Module242 AC_IDLE Comparator24

262ATmega329/3290/649/64902552H–AVR–11/06207 NEGSEL_0206 PASSEN205 PRECH204 ST203 VCCREN202 PE0.Data Port E201 PE0.Control200 PE0.Pull-up_Enable199 PE

263ATmega329/3290/649/64902552H–AVR–11/06171 PB0.Control170 PB0.Pull-up_Enable169 PB1.Data168 PB1.Control167 PB1.Pull-up_Enable166 PB2.Data165 PB2.Con

264ATmega329/3290/649/64902552H–AVR–11/06135 EXTCLK (XTAL1) Clock input and Oscillators for the main clock(Observe-only)134 OSCCK133 RCCK132 OSC32CK13

265ATmega329/3290/649/64902552H–AVR–11/0699 PD5.Pull-up_Enable98 PD6.Data97 PD6.Control96 PD6.Pull-up_Enable95 PD7.Data94 PD7.Control93 PD7.Pull-up_En

266ATmega329/3290/649/64902552H–AVR–11/0663 PH1.Pull-up_Enable62 PH2.Data61 PH2.Control60 PH2.Pull-up_Enable59 PH3.Data58 PH3.Control57 PH3.Pull-up_En

267ATmega329/3290/649/64902552H–AVR–11/06Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.Boundary-scan Description Language FilesBoundary

268ATmega329/3290/649/64902552H–AVR–11/06Boot Loader Support – Read-While-Write Self-ProgrammingThe Boot Loader Support provides a real Read-While-Wri

269ATmega329/3290/649/64902552H–AVR–11/06Note that the user software can never read any code that is located inside the RWWsection during a Boot Loade

27ATmega329/3290/649/64902552H–AVR–11/06Figure 13. Crystal Oscillator ConnectionsThe Oscillator can operate in three different modes, each optimized

270ATmega329/3290/649/64902552H–AVR–11/06Figure 118. Memory SectionsNote: 1. The parameters in the figure above are given in Table 120 on page 280.Bo

271ATmega329/3290/649/64902552H–AVR–11/06Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0” means programmedEnt

272ATmega329/3290/649/64902552H–AVR–11/06SPMCSR – Store Program Memory Control and Status RegisterThe Store Program Memory Control and Status Register

273ATmega329/3290/649/64902552H–AVR–11/06the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear uponcompletion of a Page Eras

274ATmega329/3290/649/64902552H–AVR–11/06Figure 119. Addressing the Flash During SPM(1)Note: 1. The different variables used in Figure 119 are listed

275ATmega329/3290/649/64902552H–AVR–11/06Performing Page Erase by SPMTo execute Page Erase, set up the address in the Z-pointer, write “X0000011” toSP

276ATmega329/3290/649/64902552H–AVR–11/06Setting the Boot Loader Lock Bits by SPMTo set the Boot Loader Lock bits and general Lock bits, write the des

277ATmega329/3290/649/64902552H–AVR–11/06the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destina-tion register as shown be

278ATmega329/3290/649/64902552H–AVR–11/06Simple Assembly Code Example for a Boot Loader;-the routine writes one page of data from RAM to Flash; the fi

279ATmega329/3290/649/64902552H–AVR–11/06sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256brne Rdloop; return to RWW section; verify that RWW sect

28ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device,

280ATmega329/3290/649/64902552H–AVR–11/06ATmega329/3290/649/6490Boot Loader ParametersIn Table 120 through Table 122, the parameters used in the descr

281ATmega329/3290/649/64902552H–AVR–11/06Memory ProgrammingProgram And Data Memory Lock BitsThe ATmega329/3290/649/6490 provides six Lock bits which c

282ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.2. “1” means unprogramm

283ATmega329/3290/649/64902552H–AVR–11/06Note: 1. The SPIEN Fuse is not accessible in serial programming mode.2. The default value of BOOTSZ1..0 resul

284ATmega329/3290/649/64902552H–AVR–11/06The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits arelocked if Lock bit1 (LB

285ATmega329/3290/649/64902552H–AVR–11/06Figure 120. Parallel ProgrammingTable 128. Pin Name MappingSignal Name in Programming Mode Pin Name I/O Fun

286ATmega329/3290/649/64902552H–AVR–11/06Table 130. XA1 and XA0 CodingXA1 XA0 Action when XTAL1 is Pulsed0 0 Load Flash or EEPROM Address (High or lo

287ATmega329/3290/649/64902552H–AVR–11/06Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in Parallel (High-voltage)

288ATmega329/3290/649/64902552H–AVR–11/064. Give XTAL1 a positive pulse. This loads the command.5. Give WR a negative pulse. This starts the Chip Eras

289ATmega329/3290/649/64902552H–AVR–11/06H. Program Page1. Give WR a negative pulse. This starts programming of the entire page of data.RDY/BSY goes l

29ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. The device is shipped with this option selected.2. The frequency ranges are preliminary values. Actu

290ATmega329/3290/649/64902552H–AVR–11/06Figure 122. Programming the Flash Waveforms(1)Note: 1. “XX” is don’t care. The letters refer to the programm

291ATmega329/3290/649/64902552H–AVR–11/06Figure 123. Programming the EEPROM WaveformsReading the Flash The algorithm for reading the Flash memory is

292ATmega329/3290/649/64902552H–AVR–11/06Programming the Fuse Low BitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Program

293ATmega329/3290/649/64902552H–AVR–11/06Reading the Fuse and Lock BitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to “Progr

294ATmega329/3290/649/64902552H–AVR–11/06Parallel Programming CharacteristicsFigure 126. Parallel Programming Timing, Including some General TimingRe

295ATmega329/3290/649/64902552H–AVR–11/06Figure 128. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)N

296ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2.

297ATmega329/3290/649/64902552H–AVR–11/06Serial Programming AlgorithmWhen writing serial data to the ATmega329/3290/649/6490, data is clocked on the r

298ATmega329/3290/649/64902552H–AVR–11/068. Power-off sequence (if needed):Set RESET to “1”.Tur n VCC power off.Figure 130. Serial Programming Wavef

299ATmega329/3290/649/64902552H–AVR–11/06Serial Programming Instruction setTable 137 and Figure 131 on page 300 describes the Instruction set.Table 13

3ATmega329/3290/649/64902552H–AVR–11/06Figure 2. Pinout ATmega329/649Note: The large center pad underneath the QFN/MLF packages is made of metal and

30ATmega329/3290/649/64902552H–AVR–11/06External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 14.

300ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. Not all instructions are applicable for all parts2. a = address3. Bits are programmed ‘0’, unprogra

301ATmega329/3290/649/64902552H–AVR–11/06Programming via the JTAG InterfaceProgramming through the JTAG interface requires control of the four JTAG sp

302ATmega329/3290/649/64902552H–AVR–11/06Figure 132. State Machine Sequence for Changing the Instruction WordAVR_RESET (0xC) The AVR specific public

303ATmega329/3290/649/64902552H–AVR–11/06PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via theJTAG po

304ATmega329/3290/649/64902552H–AVR–11/06Reset Register The Reset Register is a Test Data Register used to reset the part during programming. Itis req

305ATmega329/3290/649/64902552H–AVR–11/06Table 138. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte,

306ATmega329/3290/649/64902552H–AVR–11/065c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx5d. Read Data Byte 0110011_bbbbbbbb0110010_0000000

307ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command se

308ATmega329/3290/649/64902552H–AVR–11/06Figure 135. State Machine Sequence for Changing/Reading the Data WordFlash Data Byte Register The Flash Data

309ATmega329/3290/649/64902552H–AVR–11/06including the first read byte. This ensures that the first data is captured from the firstaddress set up by P

31ATmega329/3290/649/64902552H–AVR–11/06Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. Thismode is su

310ATmega329/3290/649/64902552H–AVR–11/06Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing ChipErase”

311ATmega329/3290/649/64902552H–AVR–11/06ending with the MSB of the last instruction in the page (Flash). The Capture-DRstate both captures the data f

312ATmega329/3290/649/64902552H–AVR–11/06Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS.2. Enable Lock bit write using programming

313ATmega329/3290/649/64902552H–AVR–11/06Electrical CharacteristicsAbsolute Maximum Ratings*DC CharacteristicsOperating Temperature...

314ATmega329/3290/649/64902552H–AVR–11/06Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest

315ATmega329/3290/649/64902552H–AVR–11/06External Clock Drive WaveformsFigure 137. External Clock Drive WaveformsExternal Clock DriveMaximum Speed vs

316ATmega329/3290/649/64902552H–AVR–11/06Figure 139. Maximum Frequency vs. VCC (8 - 16 MHz).SPI Timing CharacteristicsSee Figure 140 and Figure 141 f

317ATmega329/3290/649/64902552H–AVR–11/06Figure 140. SPI Interface Timing Requirements (Master Mode)Figure 141. SPI Interface Timing Requirements (S

318ATmega329/3290/649/64902552H–AVR–11/06ADC Characteristics – Preliminary DataTable 141. ADC CharacteristicsSymbol Parameter Condition Min Typ Max U

319ATmega329/3290/649/64902552H–AVR–11/06Note: 1. Voltage difference between channels.LCD Controller Characteristics – Preliminary Data – TBDCalibrate

32ATmega329/3290/649/64902552H–AVR–11/06The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-grammed, the CLKPS bits wil

320ATmega329/3290/649/64902552H–AVR–11/06ATmega329/3290/649/6490 Typical Characteristics – Preliminary DataThe following charts show typical behavior.

321ATmega329/3290/649/64902552H–AVR–11/06Figure 143. Active Supply Current vs. Frequency (1 - 16 MHz))Figure 144. Active Supply Current vs. VCC (Int

322ATmega329/3290/649/64902552H–AVR–11/06Figure 145. Active Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1 MHz)Figure 146. Act

323ATmega329/3290/649/64902552H–AVR–11/06Idle Supply Current Figure 147. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)Figure 148. Idle Supply Cu

324ATmega329/3290/649/64902552H–AVR–11/06Figure 149. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)Figure 150. Idle Supply Current vs.

325ATmega329/3290/649/64902552H–AVR–11/06Figure 151. Idle Supply Current vs. VCC (32 kHz External Oscillator)Supply Current of I/O modules The tables

326ATmega329/3290/649/64902552H–AVR–11/06It is possible to calculate the typical current consumption based on the numbers fromTable 145 for other VCC

327ATmega329/3290/649/64902552H–AVR–11/06Power-save Supply Current Figure 154. Power-save Supply Current vs. VCC (Watchdog Timer Disabled)Standby Sup

328ATmega329/3290/649/64902552H–AVR–11/06Pin Pull-up Figure 156. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)Figure 157. I/O Pin Pu

329ATmega329/3290/649/64902552H–AVR–11/06Figure 158. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)Figure 159. Reset Pull-up Resist

33ATmega329/3290/649/64902552H–AVR–11/06Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, the

330ATmega329/3290/649/64902552H–AVR–11/06Figure 160. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)Figure 161. Reset Pull-up Resi

331ATmega329/3290/649/64902552H–AVR–11/06Pin Driver Strength Figure 162. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J(VCC=

332ATmega329/3290/649/64902552H–AVR–11/06Figure 164. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J(VCC=1.8V)Figure 165. I/

333ATmega329/3290/649/64902552H–AVR–11/06Figure 166. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V)Figure 167. I/O Pin Source Curren

334ATmega329/3290/649/64902552H–AVR–11/06Figure 168. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V)Figure 169. I/O

335ATmega329/3290/649/64902552H–AVR–11/06Figure 170. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J(VCC = 1.8V)Figure 171. I/

336ATmega329/3290/649/64902552H–AVR–11/06Figure 172. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V)Figure 173. I/O Pin Sink Current vs

337ATmega329/3290/649/64902552H–AVR–11/06Pin Thresholds and hysteresis Figure 174. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)

338ATmega329/3290/649/64902552H–AVR–11/06Figure 176. I/O Pin Input Hysteresis vs. VCCFigure 177. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pi

339ATmega329/3290/649/64902552H–AVR–11/06Figure 178. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”)Figure 179. Reset Input Pin Hy

34ATmega329/3290/649/64902552H–AVR–11/06Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle mode, stoppin

340ATmega329/3290/649/64902552H–AVR–11/06BOD Thresholds and Analog Comparator OffsetFigure 180. BOD Thresholds vs. Temperature (BOD Level is 4.3V)Fig

341ATmega329/3290/649/64902552H–AVR–11/06Figure 182. BOD Thresholds vs. Temperature (BOD Level is 1.8V)Figure 183. Bandgap Voltage vs. VCC BOD THRES

342ATmega329/3290/649/64902552H–AVR–11/06Figure 184. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)Figure 185. Analog Comparato

343ATmega329/3290/649/64902552H–AVR–11/06Internal Oscillator Speed Figure 186. Watchdog Oscillator Frequency vs. VCC Figure 187. Calibrated 8 MHz RC

344ATmega329/3290/649/64902552H–AVR–11/06Figure 188. Calibrated 8 MHz RC Oscillator Frequency vs. VCC Figure 189. Calibrated 8 MHz RC Oscillator Fre

345ATmega329/3290/649/64902552H–AVR–11/06Current Consumption of Peripheral UnitsFigure 190. Brownout Detector Current vs. VCC Figure 191. ADC Curren

346ATmega329/3290/649/64902552H–AVR–11/06Figure 192. AREF External Reference Current vs. VCC Figure 193. 32 kHZ TOSC Current vs. VCC (Watchdog Timer

347ATmega329/3290/649/64902552H–AVR–11/06Figure 194. Watchdog Timer Current vs. VCC Figure 195. Analog Comparator Current vs. VCC WATCHDOG TIMER CUR

348ATmega329/3290/649/64902552H–AVR–11/06Figure 196. Programming Current vs. VCC Current Consumption in Reset and Reset PulsewidthFigure 197. Reset

349ATmega329/3290/649/64902552H–AVR–11/06Figure 198. Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current Through TheReset Pull-up)Figure 199.

35ATmega329/3290/649/64902552H–AVR–11/06The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn-chronously in Power-save mode

350ATmega329/3290/649/64902552H–AVR–11/06Register Summary Note: Registers with bold type only available in ATmega3290/6490.Address Name Bit 7 Bit 6 Bi

351ATmega329/3290/649/64902552H–AVR–11/06(0xC2)UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 181(0xC1)UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0

352ATmega329/3290/649/64902552H–AVR–11/06(0x83)Reserved - - - - - - - -(0x82)TCCR1C FOC1A FOC1B - - - - - -129(0x81)TCCR1B ICNC1 ICES1 - WGM13WGM12CS1

353ATmega329/3290/649/64902552H–AVR–11/06Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved

354ATmega329/3290/649/64902552H–AVR–11/06Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTION

355ATmega329/3290/649/64902552H–AVR–11/06BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2BRID k Branch if Interrupt Disa

356ATmega329/3290/649/64902552H–AVR–11/06POP Rd Pop Register from Stack Rd ← STACK None 2MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (s

357ATmega329/3290/649/64902552H–AVR–11/06Ordering InformationNotes: 1. This device can also be supplied in wafer form. Please contact your local Atmel

358ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for de

359ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for de

36ATmega329/3290/649/64902552H–AVR–11/06Minimizing Power ConsumptionThere are several possibilities to consider when trying to minimize the power cons

360ATmega329/3290/649/64902552H–AVR–11/06Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for de

361ATmega329/3290/649/64902552H–AVR–11/06Packaging Information64A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 64A, 64-lead, 14 x

362ATmega329/3290/649/64902552H–AVR–11/0664M1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead

363ATmega329/3290/649/64902552H–AVR–11/06100A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 100A, 100-lead, 14 x 14 mm Body Size, 1

364ATmega329/3290/649/64902552H–AVR–11/06ErrataATmega329 rev. C• Interrupts may be lost when writing the timer registers in the asynchronous timer1. I

365ATmega329/3290/649/64902552H–AVR–11/06ATmega3290 rev. C• Interrupts may be lost when writing the timer registers in the asynchronous timer1. Interr

366ATmega329/3290/649/64902552H–AVR–11/06ATmega649 rev. A• Interrupts may be lost when writing the timer registers in the asynchronous timer1. Interru

367ATmega329/3290/649/64902552H–AVR–11/06Datasheet Revision HistoryPlease note that the referring page numbers in this section are referring to this d

368ATmega329/3290/649/64902552H–AVR–11/06Rev. 2552B – 05/05Rev. 2552A –11/041. MLF-package alternative changed to “Quad Flat No-Lead/Micro LeadFrame P

iATmega329/3290/649/64902552H–AVR–11/06Table of Contents Features...

37ATmega329/3290/649/64902552H–AVR–11/06ters (DIDR1 and DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page202 and “DIDR0 – Digital In

iiATmega329/3290/649/64902552H–AVR–11/06Idle Mode ...

iiiATmega329/3290/649/64902552H–AVR–11/06Modes of Operation ...

ivATmega329/3290/649/64902552H–AVR–11/06Starting a Conversion ...

vATmega329/3290/649/64902552H–AVR–11/06Calibration Byte ...

viATmega329/3290/649/64902552H–AVR–11/06Datasheet Revision History ... 367Rev. 2552H – 11/06.

2552H–AVR–11/06Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel

38ATmega329/3290/649/64902552H–AVR–11/06Register DescriptionSMCR – Sleep Mode Control RegisterThe Sleep Mode Control Register contains control bits fo

39ATmega329/3290/649/64902552H–AVR–11/06Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping theclock to the module. W

4ATmega329/3290/649/64902552H–AVR–11/06OverviewThe ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC ar

40ATmega329/3290/649/64902552H–AVR–11/06System Control and ResetResetting the AVR During reset, all I/O Registers are set to their initial values, and

41ATmega329/3290/649/64902552H–AVR–11/06Figure 15. Reset LogicNotes: 1. The Power-on Reset will not work unless the supply voltage has been below VPO

42ATmega329/3290/649/64902552H–AVR–11/06Figure 16. MCU Start-up, RESET Tied to VCCFigure 17. MCU Start-up, RESET Extended ExternallyExternal Reset A

43ATmega329/3290/649/64902552H–AVR–11/06teresis to ensure spike free Brown-out Detection. The hysteresis on the detection levelshould be interpreted a

44ATmega329/3290/649/64902552H–AVR–11/06Figure 20. Watchdog Reset During OperationMCUSR – MCU Status RegisterThe MCU Status Register provides informa

45ATmega329/3290/649/64902552H–AVR–11/06Internal Voltage ReferenceATmega329/3290/649/6490 features an internal bandgap reference. This reference isuse

46ATmega329/3290/649/64902552H–AVR–11/06Figure 21. Watchdog TimerWDTCR – Watchdog Timer Control Register• Bits 7:5 – Res: Reserved BitsThese bits are

47ATmega329/3290/649/64902552H–AVR–11/06The following code example shows one assembly and one C function for turning off theWDT. The example assumes t

48ATmega329/3290/649/64902552H–AVR–11/06Timed Sequences for Changing the Configuration of the Watchdog TimerThe sequence for changing configuration di

49ATmega329/3290/649/64902552H–AVR–11/06Interrupts This section describes the specifics of the interrupt handling as performed inATmega329/3290/649/64

5ATmega329/3290/649/64902552H–AVR–11/06The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are

50ATmega329/339/649/6592552H–AVR–11/06Table 23 shows reset and Interrupt Vectors placement for the various combinations ofBOOTRST and IVSEL settings.

51ATmega329/339/649/6592552H–AVR–11/06When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes andthe IVSEL bit in the MCUCR Regis

52ATmega329/339/649/6592552H–AVR–11/060x382E/0x782ERESET:ldir16,high(RAMEND); Main program start0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top o

53ATmega329/339/649/6592552H–AVR–11/06Assembly Code ExampleMove_interrupts:;Get MCUCRin r16, MCUCRmov r17, r16; Enable change of Interrupt Vectorsori

54ATmega329/3290/649/64902552H–AVR–11/06External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins.Observ

55ATmega329/3290/649/64902552H–AVR–11/06EICRA – External Interrupt Control Register AThe External Interrupt Control Register A contains control bits f

56ATmega329/3290/649/64902552H–AVR–11/06External Interrupt Mask Register – EIMSK• Bit 7 – PCIE3: Pin Change Interrupt Enable 3When the PCIE3 bit is se

57ATmega329/3290/649/64902552H–AVR–11/06EIFR – External Interrupt Flag Register• Bit 7 – PCIF3: Pin Change Interrupt Flag 3When a logic change on any

58ATmega329/3290/649/64902552H–AVR–11/06PCMSK2 – Pin Change Mask Register 2(1)• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16Each PCINT23:16 bit

59ATmega329/3290/649/64902552H–AVR–11/06I/O-PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O

6ATmega329/3290/649/64902552H–AVR–11/06Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490The ATmega329, ATmega3290, ATmega649, and ATm

60ATmega329/3210/649/64102552H–AVR–11/06in “Alternate Port Functions” on page 65. Refer to the individual module sections for afull description of the

61ATmega329/3210/649/64102552H–AVR–11/06If PORTxn is written logic one when the pin is configured as an output pin, the port pin isdriven high (one).

62ATmega329/3210/649/64102552H–AVR–11/06Figure 25. Synchronization when Reading an Externally Applied Pin valueXXX in r17, PINx0x00 0xFFINSTRUCTIONSS

63ATmega329/3210/649/64102552H–AVR–11/06Consider the clock period starting shortly after the first falling edge of the system clock.The latch is close

64ATmega329/3210/649/64102552H–AVR–11/06Note: 1. For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set

65ATmega329/3210/649/64102552H–AVR–11/06described above, floating inputs should be avoided to reduce current consumption in allother modes where the d

66ATmega329/3210/649/64102552H–AVR–11/06Table 26 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 27 are not sho

67ATmega329/3210/649/64102552H–AVR–11/06MCUCR – MCU Control Register• Bit 4 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the

68ATmega329/3210/649/64102552H–AVR–11/06Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 30.The alternate pin

69ATmega329/3210/649/64102552H–AVR–11/06PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter-rupt source.• OC1B/PCINT14

7ATmega329/3290/649/64902552H–AVR–11/06Port D also serves the functions of various special features of theATmega329/3290/649/6490 as listed on page 73

70ATmega329/3210/649/64102552H–AVR–11/06•SS/PCINT8 – Port B, Bit 0SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configu

71ATmega329/3210/649/64102552H–AVR–11/06 Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller.The alternat

72ATmega329/3210/649/64102552H–AVR–11/06Table 34. Overriding Signals for Alternate Functions in PC7:PC4Signal Name PC7/SEG5 PC6/SEG6 PC5/SEG(11/7) PC

73ATmega329/3210/649/64102552H–AVR–11/06Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 36.The alternate pin

74ATmega329/3210/649/64102552H–AVR–11/06 Table 37. Overriding Signals for Alternate Functions PD7:PD4Signal Name PD7/SEG(19/15) PD6/SEG(20/16) PD5/SE

75ATmega329/3210/649/64102552H–AVR–11/06Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39.• PCINT7 – Port E

76ATmega329/3210/649/64102552H–AVR–11/06• XCK/AIN0/PCINT2 – Port E, Bit 2XCK, USART0 External Clock. The Data Direction Register (DDE2) controls wheth

77ATmega329/3210/649/64102552H–AVR–11/06 Note: 1. AIN0D and AIN1D is described in “DIDR1 – Digital Input Disable Register 1” on page202.Alternate Func

78ATmega329/3210/649/64102552H–AVR–11/06• TDO, ADC6 – Port F, Bit 6ADC6, Analog to Digital Converter, Channel 6.TDO, JTAG Test Data Out: Serial output

79ATmega329/3210/649/64102552H–AVR–11/06 Alternate Functions of Port G The alternate pin configuration is as follows:Note: 1. Port G, PG5 is input onl

8ATmega329/3290/649/64902552H–AVR–11/06XTAL2 Output from the inverting Oscillator amplifier.AVCC AVCC is the supply voltage pin for Port F and the A/D

80ATmega329/3210/649/64102552H–AVR–11/06• SEG – Port G, Bit 1SEG, Segment driver 17/13.• SEG – Port G, Bit 0SEG, LCD front plane 18/14.Table 45 and Ta

81ATmega329/3210/649/64102552H–AVR–11/06Alternate Functions of Port H Port H is only present in ATmega3290/6490. The alternate pin configuration is as

82ATmega329/3210/649/64102552H–AVR–11/06• PCINT17/SEG – Port H, Bit 1PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external inte

83ATmega329/3210/649/64102552H–AVR–11/06Alternate Functions of Port J Port J is only present in ATmega3290/6490. The alternate pin configuration is as

84ATmega329/3210/649/64102552H–AVR–11/06• PCINT28/SEG – Port J, Bit 4PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external in

85ATmega329/3210/649/64102552H–AVR–11/06Table 53. Overriding Signals for Alternate Functions in PH3:0Signal NamePJ3/PCINT27/SEG30PJ2/PCINT26/SEG31PJ1

86ATmega329/3210/649/64102552H–AVR–11/06Register Description for I/O-PortsPORTA – Port A Data RegisterDDRA – Port A Data Direction RegisterPINA – Port

87ATmega329/3210/649/64102552H–AVR–11/06PORTD – Port D Data RegisterDDRD – Port D Data Direction RegisterPIND – Port D Input Pins AddressPORTE – Port

88ATmega329/3210/649/64102552H–AVR–11/06PORTG – Port G Data RegisterDDRG – Port G Data Direction RegisterPING – Port G Input Pins AddressPORTH – Port

89ATmega329/3290/649/64902552H–AVR–11/068-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter mod

9ATmega329/3290/649/64902552H–AVR–11/06AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theC

90ATmega329/3290/649/64902552H–AVR–11/06event will also set the Compare Flag (OCF0A) which can be used to generate an OutputCompare interrupt request.

91ATmega329/3290/649/64902552H–AVR–11/06Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer cl

92ATmega329/3290/649/64902552H–AVR–11/06The OCR0A Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal

93ATmega329/3290/649/64902552H–AVR–11/06Figure 31. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the Output Comp

94ATmega329/3290/649/64902552H–AVR–11/06Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins,

95ATmega329/3290/649/64902552H–AVR–11/06to OCR0A is lower than the current value of TCNT0, the counter will miss the comparematch. The counter will th

96ATmega329/3290/649/64902552H–AVR–11/06The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. Ifthe interrupt is enabled, t

97ATmega329/3290/649/64902552H–AVR–11/06Figure 34. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV0) is set each time the

98ATmega329/3290/649/64902552H–AVR–11/06• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare

99ATmega329/3290/649/64902552H–AVR–11/06Figure 38 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.Figure 38. Timer/Counter Timing Di