
ATmega603/103
86
Figure 64. Port D Schematic Diagram (Pin PD5)
Figure 65. Port D Schematic Diagram (Pins PD6 and PD7)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD5
R
R
WP:
WD:
RL:
RP:
RD:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
DDD5
PORTD5
RL
RP
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PDn
R
R
WP:
WD:
RL:
RP:
RD:
n:
m:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
6, 7
1, 2
DDDn
PORTDn
SENSE CONTROL
TIMERm CLOCK
SOURCE MUX
CSm2
CSm0
RL
RP
CSm1
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