Rainbow-electronics ATmega3290P_V Instrukcja Użytkownika Pobierz pdf (Strona 98)

100

101

ATmega329/3290/649/6490

2552H–AVR–11/06

• The timer starts counting from a value higher than the one in OCR0A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set. Figure 35 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 35. Timer/Counter Timing Diagram, no Prescaling

Figure 36 shows the same timing data, but with the prescaler enabled.

Figure 36. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

Figure 37 shows the setting of OCF0A in all modes except CTC mode.

Figure 37. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f

clk_I/O

/8)

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clk

I/O

/8)

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 374 375

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