Rainbow-electronics ATmega3290P_V Instrukcja Użytkownika Pobierz pdf (Strona 142)

100

101

142

ATmega329/3290/649/6490

2552H–AVR–11/06

• The timer starts counting from a value higher than the one in OCR2A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock

(clk

) is therefore shown as a clock enable signal. In asynchronous mode, clk

I/O

should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when Interrupt Flags are set. Figure 61 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 61. Timer/Counter Timing Diagram, no Prescaling

Figure 62 shows the same timing data, but with the prescaler enabled.

Figure 62. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

Figure 63 shows the setting of OCF2A in all modes except CTC mode.

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

1 2 ... 137 138 139 140 141 142 143 144 145 146 147 ... 374 375

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