Rainbow-electronics ATmega64C1 Instrukcja Użytkownika Pobierz pdf (Strona 156)

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7647A–AVR–02/08

ATmega32/64/M1/C1

• Bit 2 – PEV1 : PSC External Event 1 Interrupt

This bit is set by hardware when an external event which can generates a fault on module 1

occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVE1 bit = 0).

• Bit 1 – PEV0 : PSC External Event 0 Interrupt

This bit is set by hardware when an external event which can generates a fault on module 0

occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVE0 bit = 0).

• Bit 0 – PEOP : PSC End Of Cycle Interrupt

This bit is set by hardware when an “end of PSC cycle” occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEOPE bit = 0).

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