
220
7647A–AVR–02/08
ATmega32/64/M1/C1
17.6 LIN / UART Register Description
17.6.1 LIN Control Register - LINCR
• Bit 7 - LSWRES: Software Reset
– 0 = No action,
– 1 = Software reset (this bit is self-reset at the end of the reset procedure).
• Bit 6 - LIN13: LIN 1.3 mode
– 0 = LIN 2.1 (default),
– 1 = LIN 1.3.
• Bit 5:4 - LCONF[1:0]: Configuration
a. LIN mode (default = 00):
–00 = LIN Standard configuration (listen mode “off”, CRC “on” & Frame_Time_Out “on”,
– 01 = No CRC, no Time out (listen mode “off”),
Table 17-5. LIN/UART Register Bits Summary
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LINCR
LSWRES LIN13 LCONF1 LCONF0 LENA LCMD2 LCMD1 LCMD0
0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
LINSIR
LIDST2 LIDST1 LIDST0 LBUSY LERR LIDOK LTXOK LRXOK
0R0R0R0R0R/W
one
0R/W
one
0R/W
one
0R/W
one
LINENIR
————LENERRLENIDOKLENTXOKLENRXOK
0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W
LINERR
LABORT LTOERR LOVERR LFERR LSERR LPERR LCERR LBERR
0R0R0R0R0R0R0R0R
LINBTR
LDISR LBT5 LBT4 LBT3 LBT2 LBT1 LBT0
0 R/W 0 R 1 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W)
LINBRRL
LDIV7LDIV6LDIV5LDIV4LDIV3LDIV2LDIV1LDIV0
0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
LINBRRH
————LDIV11LDIV10LDIV9LDIV8
0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W
LINDLR
LTXDL3 LTXDL2 LTXDL1 LTXDL0 LRXDL3 LRXDL2 LRXDL1 LRXDL0
0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
LINIDR
LP1 LP0 LID5/LDL1 LID4/LDL0 LID3 LID2 LID1 LID0
1 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
LINSEL
————LAINCLINDX2 LINDX1 LINDX0
0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W
LINDAT
LDATA7 L DATA6 L DATA 5 L DATA 4 L DATA 3 LDATA2 L DATA1 L DATA0
0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 76543210
LSWRES LIN13 LCONF1 LCONF0 LENA LCMD2 LCMD1 LCMD0
LINCR
Read/Write R/W R/W R/W R/W R R/W R/W R/W
Initial Value00000000
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