
248
7647A–AVR–02/08
ATmega32/64/M1/C1
Figure 18-16. Amplifier synchronization timing diagram
With change on analog input signal
Valid sample
Delta V
4th stable sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC
PSCn_ASY
PSC
Block
ADSC
ADC
Activity
ADC
ADC
Sampling
ADC
Co n v
ADC
Sampling
ADC
Co n v
ADC Result
Ready
ADC Resul
Ready
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