Rainbow-electronics W90P710CDG Instrukcja Użytkownika Pobierz pdf (Strona 132)

100

101

W90P710CD/W90P710CDG

- 132 -

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

RXMS

7 6 5 4 3 2 1 0

RXMS

BITS DESCRIPTIONS

[31:16] Reserved -

[15:0] RXMS

The Maximum Receive Frame Length defines the

maximum frame length for received frame. If the frame

length of received frame is greater than RXMS, and bit

EnDFO of MIEN register is also enabled, the bit DFOI of

MISTA register is set and the Rx interrupt is triggered.

It is recommended that only use RXMS to qualify the length

of received frame while S/W wants to receive a frame which

length is greater than 1518 bytes.

MAC Interrupt Enable Register (MIEN)

The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR

for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.

MIEN 0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved EnTxBErr

23 22 21 20 19 18 17 16

EnTDU EnLC EnTXABT EnNCS EnEXDEF EnTXCP EnTXEMP EnTXINTR

15 14 13 12 11 10 9 8

Reserved EnCFR Reserved EnRxBErr EnRDU EnDEN EnDFO

7 6 5 4 3 2 1 0

EnMMP EnRP EnALIE EnRXGD EnPTLE EnRXOV EnCRCE EnRXINTR

1 2 ... 127 128 129 130 131 132 133 134 135 136 137 ... 551 552

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