Rainbow-electronics W90P710CDG Instrukcja Użytkownika Pobierz pdf (Strona 166)

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W90P710CD/W90P710CDG

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BITS DESCRIPTIONS

[4] DADIR

Destination Address Direction

1’b0 = Destination address is incremented successively

1’b1 = Destination address is decremented successively

[3:2] GDMAMS

GDMA Mode Select

00 = Software mode (memory-to-memory)

01 = External nXDREQ mode for external device

10 = Reserved

11 = Reserved

[1] Reserved

[0] GDMAEN

GDMA Enable

1’b0 = Disables the GDMA operation

1’b1 = Enables the GDMA operation; this bit will be clear automatically

when the transfer is complete on AUTOIEN [19] register bit is on Disable

mode.

Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1)

The GDMA channel starts reading its data from the source address as defined in this source base

address register.

GDMA_SRCB0 0xFFF0_4004 R/W

Channel 0 Source Base Address Register

0x0000_0000

GDMA_SRCB1 0xFFF0_4024 R/W

Channel 1 Source Base Address Register

0x0000_0000

31 30 29 28 27 26 25 24

SRC_BASE_ADDR [31:24]

23 22 21 20 19 18 17 16

SRC_BASE_ADDR [23:16]

15 14 13 12 11 10 9 8

SRC_BASE_ADDR [15:8]

7 6 5 4 3 2 1 0

SRC_BASE_ADDR [7:0]

BITS DESCRIPTIONS

[31:0] SRC_BASE_ADDR 32-bit Source Base Address

1 2 ... 161 162 163 164 165 166 167 168 169 170 171 ... 551 552

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