Rainbow-electronics ATmega128RFA1 Instrukcja Użytkownika Pobierz pdf (Strona 170)

170

8266A-MCU Wireless-12/09

ATmega128RFA1

12.6.6 DRTRAM0 – Data Retention Configuration Register of SRAM 0

Bit 7 6 5 4 3 2 1 0

NA ($135) Res1 Res0 DRTSWOK

ENDRT Resx3 Resx2 Resx1 Resx0 DRTRAM0

Read/Write R R R RW RW RW RW RW

Initial Value 0 0 0 0 0 0 0 0

The DRTRAM0 register controls the behavior of SRAM block 0 in the power-states

"power-save" and "power-down". To prevent any data loss the SRAM will not

completely disconnected from the power supply. Reserved bits will be overwritten

during chip reset by the factory calibration and should not be modified.

• Bit 7:6 – Res1:0 - Reserved

• Bit 5 – DRTSWOK - DRT Switch OK

This bit indicates the status of the SRAM power-switch. A logical one indicates that the

SRAM supply voltage is fully available and the memory may be accessed normally.

• Bit 4 – ENDRT - Enable SRAM Data Retention

During "Deep-Sleep" each SRAM block will either be switched off or provides data

retention of its memory content. This bit must set to one if data retention mode should

be used. Otherwise the SRAM is switched off (disconnected from the power supply)

and all its data are lost.

• Bit 3:0 – Resx3:0 - Reserved

12.6.7 DRTRAM1 – Data Retention Configuration Register of SRAM 1

Bit 7 6 5 4 3 2 1 0

NA ($134) Res1 Res0 DRTSWOK

ENDRT Resx3 Resx2 Resx1 Resx0 DRTRAM1