Rainbow-electronics ATmega8515L Instrukcja Użytkownika Pobierz pdf (Strona 123)

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ATmega8515(L)

2512A–AVR–04/02

Serial Peripheral

Interface–SPI

The Serial PeripheralInterface (SPI) allows high-speedsynchronousdata transfer

between the ATmega8515 andperipheraldevices orbetween several AVR devices.

The ATmega8515 SPI includes the following features:

•

Full Duplex, 3-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Figure 59. SPIBlock Diagram

(1)

Note: 1. Refer to Figure1onpage 2, and Table29 on page 64 forSPIpin placement.

Theinterconnection between Master andSlave CPUs withSPI isshowninFigure 60.

The system consists of two Shift Registers, and a Masterclock generator.The SPIMas-

ter initiates the communication cycle when pulling low the Slave Select SS

pin of the

desiredSlave. Master andSlave preparethe data to be sent in theirrespective Shift

Registers, and the Master generates the requiredclock pulses on the SCK linetointer-

change data. Data is always shiftedfrom Master to Slaveonthe MasterOut – Slave In,

MOSI, line, andfrom Slave to Master on the MasterIn–Slave Out,MISO,line. After

each data packet, the Masterwill synchronizethe Slave by pulling high the Slave Select,

,line.

SPI2X

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