
197
ATmega8515(L)
2512A–AVR–04/02
SPI Timing
Characteristics
See Figure87 andFigure88fordetails.
Figure 87. SPIInterface Timing Requirements(MasterMode)
Table 98. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK periodMasterSee Table58
ns
2 SCK high/lowMaster 50%duty cycle
3 Rise/Fall time Master TBD
4 SetupMaster 10
5 Hold Master 10
6Out to SCK Master 0.5 • t
SCK
7SCKto out Master 10
8 SCK to out highMaster 10
9SSlow to out Slave 15
10 SCK periodSlave 4 • t
ck
11 SCK high/lowSlave 2 • t
ck
12 Rise/Fall time Slave TBD
13SetupSlave 10
14 Hold Slave 10
15 SCK to out Slave 15
16SCKto SS
highSlave 20
17SS
high to tri-state Slave 10
18 SS
low to SCK Salve 2 • t
ck
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7
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