Rainbow-electronics ATmega8515L Instrukcja Użytkownika Strona 91

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91
ATmega8515(L)
2512A–AVR–04/02
Timer/Counter Interrupt Flag
Register – TIFR
Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 isset (one)when an overflow occurs in Timer/Counter0. TOV0 iscleared
by hardware when executing the corresponding interrupt handling vector.Alternatively,
TOV0 isclearedbywriting a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 OverflowInterrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interruptis executed. In phase correctPWM mode, thisbit is
set when Timer/Counter0 changescounting direction at $00.
Bit0–OCF0:OutputCompareFlag0
The OCF0 bit isset (one)when a comparematch occurs between theTimer/Counter0
and the data in OCR0 Output CompareRegister0. OCF0isclearedbyhardware when
executing the corresponding interrupt handling vector.Alternatively, OCF0isclearedby
writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Com-
parematch Interrupt Enable), andOCF0are set (one), theTimer/Counter0 Compare
match Interruptis executed.
Bit 76543 210
TOV1 OCF1A OCF1B ICF1 –TOV0OCF0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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