
61
ATmega8515(L)
2512A–AVR–04/02
Alternate Port Functions Most port pinshave alternate functions in addition to being generaldigitalI/Os. Figure
32 shows how the port pin controlsignals from the simplifiedFigure29can beoverrid-
den by alternate functions.Theoverriding signals may not be present in all port pins, but
the figure serves as agenericdescription applicabletoall port pins in the AVR micro-
controllerfamily.
Figure 32. Alternate Port Functions
(1)
Note: 1. WPx, WDx, RRx, RPx, and RDx are commontoall pinswithin the same port. clk
I/O
,
SLEEP, and PUD are common to all ports.All othersignals are unique for each pin.
Table25summarizes the function of theoverriding signals.The pin andportindexes
from Figure 32are not showninthe succeeding tables.Theoverriding signals are gen-
erated internally in themoduleshaving thealternate function.
clk
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
Q
D
CLR
Q
Q
D
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA B US
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
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