151
ATmega8515(L)
2512A–AVR–04/02
Thetransmit buffercan only be written when the UDREflag in the UCSRA Register is
set. Data written to UDR when the UDREflag is not set,will be ignoredbythe USART
Transmitter. When data iswritten to thetransmit buffer, and theTransmitter is enabled,
theTransmitterwill load the data into theTransmit Shift Registerwhen the Shift Register
is empty.Then the data will be serially transmitted on theTxD pin.
The receive bufferconsists of atwo levelFIFO.The FIFO will change itsstate whenever
the receive buffer is accessed. Due to thisbehavior of the receive buffer, do not use
read modify write instructions(SBIandCBI)on thislocation. Be carefulwhen using bit
testinstructions (SBIC andSBIS),sincethesealso will change the state of the FIFO.
USART Control and Status
Register A – UCSRA
• Bit7–RXC: USART Receive Complete
Thisflag bit isset when thereareunreaddatainthe receive buffer andclearedwhen the
receive buffer is empty(i.e.,does not contain any unreaddata). If the receiver isdis-
abled, the receive bufferwill be flushed andconsequently theRXC bit will become zero.
TheRXC flag can beused to generateaReceive Complete interrupt (see description of
theRXCIE bit).
• Bit6–TXC: USART Transmit Complete
Thisflag bit isset when the entire frame in theTransmit Shift Registerhasbeen shifted
out and therearenonewdata currently present in thetransmit buffer(UDR).TheTXC
flag bit is automatically clearedwhenatransmit complete interruptis executed, or it can
be clearedbywriting a one to itsbit location. TheTXC flag can generateaTransmit
Complete interrupt (see description of theTXCIE bit).
• Bit 5 – UDRE: USART Data Register Empty
The UDREflag indicates if thetransmit buffer(UDR) isready to receive newdata. If
UDRE is one, the buffer is empty, and therefore ready to be written. The UDREflag can
generate a Data RegisterEmpty interrupt (see description of the UDRIE bit).
UDRE isset after a reset to indicate that theTransmitter isready.
• Bit4–FE:FrameError
Thisbit isset if thenext character in the receive bufferhad a Frame Errorwhen
received. For example,when the first stopbit of thenext character in the receive buffer
iszero. Thisbit is valid until the receive buffer(UDR) isread.The FE bit iszero when
the stopbit ofreceiveddata is one. Always set thisbit to zero when writing to UCSRA.
• Bit3–DOR:DataOverRun
Thisbit isset if a Data OverRun condition isdetected.AData OverRun occurs when the
receive buffer isfull (two characters), it is anewcharacterwaiting in theReceive Shift
Register, and anewstart bit isdetected.Thisbit is valid until the receive buffer(UDR) is
read.Always set thisbit to zero when writing to UCSRA.
Bit 76543 210
RXCTXC UDRE FE DOR PE U2X MPCM UCSRA
Read/Write R R/W RRRRR/W R/W
Initial Value00100000
(24 strony)
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