
189
ATmega8515(L)
2512A–AVR–04/02
Serial Downloading Both the Flash andEEPROM memory arrays can be programmed using the serialSPI
buswhileRESET
ispulled to GND.The serial interface consists ofpinsSCK,MOSI
(input) andMISO(output).After RESET
isset low, theProgramming Enableinstruction
needs to beexecutedfirst before program/eraseoperationscan beexecuted.
Note:InTable 92, the pin mapping forSPIprogramming islisted. Not all parts usethe SPIpins
dedicatedfor theinternalSPI interface.
Serial Programming Pin
Mapping
Both the Flash andEEPROM memory arrays can be programmed using the serialSPI
buswhileRESET
ispulled to GND.The serial interface consists ofpinsSCK,MOSI
(input) andMISO(output).After RESET
isset low, theProgramming Enableinstruction
needs to beexecutedfirst before program/eraseoperationscan beexecuted. NOTE, in
Table 92onpage 189, the pin mapping forSPIprogramming islisted. Not all parts use
the SPIpinsdedicatedfor theinternalSPI interface.
Figure 83. Serial Programming and Verify
(1)
Note: 1. If the deviceisclockedbytheinternal oscillator, it is no need to connectaclock
sourcetothe XTA L1 pin.
When programming the EEPROM, an auto-erase cycleisbuiltintothe self-timedpro-
gramming operation (in the Serial mode ONLY) and thereis no need to firstexecute the
ChipEraseinstruction. The ChipEraseoperation turns the content of every memory
location in both theProgram andEEPROM arrays into $FF.
Depending on CKSEL Fuses, avalidclock must be present. Theminimumlow andhigh
periods for the serialclock (SCK) input are defined asfollows:
Low: > 2 CPUclock cyclesforf
ck
< 12 MHz, 3 CPUclock cyclesforf
ck
≥ 12 MHz
High: > 2 CPUclock cyclesforf
ck
< 12 MHz, 3 CPUclock cyclesforf
ck
≥ 12 MHz
Table 92. Pin Mapping Serial Programming
Symbol Pins I/O
Description
MOSI PB5 ISerialdata in
MISO PB6 O Serialdata out
SCK PB7 I Serialclock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
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