18
ATmega8515(L)
2512A–AVR–04/02
The EEPROM Control Register
–EECR
• Bits 7..4 – Res: Reserved Bits
These bits are reservedbits in the ATmega8515 andwill always read aszero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interruptif the I-bit in SREG isset.
Writing EERIE to zero disables theinterrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEWE iscleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determineswhethersetting EEWE to one causes the EEPROM to be
written. When EEMWE isset,setting EEWE within fourclock cycleswill write data to the
EEPROM at the selected address If EEMWE iszero,setting EEWE will have no effect.
When EEMWE hasbeen written to one by software,hardware clears the bit to zeroafter
fourclock cycles. See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable SignalEEWEis the write strobetothe EEPROM. When
address anddata are correctly set up, the EEWE bit must be written to one to write the
value into the EEPROM.The EEMWE bit must be written to one beforealogical one is
written to EEWE, otherwisenoEEPROM write takesplace. The following procedure
should be followedwhen writing the EEPROM (theorder ofsteps 3 and 4is not
essential):
1. Wait untilEEWEbecomeszero.
2. Wait untilSPMEN in SPMCR becomeszero.
3. Write newEEPROM address to EEAR (optional).
4. Write newEEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zerotoEEWE in EECR.
6. Within fourclock cycles aftersetting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmedduring a CPUwritetothe Flash memory.The
softwaremust check that the Flash programming iscompletedbefore initiating a new
EEPROM write. Step 2is only relevant if the software contains a Boot Loader allowing
the CPU to program the Flash. If the Flash is neverbeing updatedbythe CPU, step 2
can be omitted. See “Boot LoaderSupport–Read-While-Write Self-Programming” on
page 162 fordetails about boot programming.
Caution: An interrupt between step 5andstep6will makethe write cycle fail, sincethe
EEPROM MasterWrite Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting anotherEEPROM access, the EEAR or EEDR Registerwill be
modified, causing theinterruptedEEPROM access to fail. Itisrecommended to have
theglobal interrupt flag clearedduring all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit isclearedbyhardware. The
usersoftware can poll thisbit andwait for a zero before writing thenext byte. When
EEWE hasbeen set, the CPU ishaltedfor two cyclesbeforethenextinstruction is
executed.
Bit 76543 210
––––EERIEEEMWEEEWEEEREEECR
Read/WriteRRRRR/W R/W R/W R/W
Initial Value000000X 0
(24 strony)
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