Rainbow-electronics ATmega8515L Instrukcja Użytkownika Pobierz pdf (Strona 152)

152

ATmega8515(L)

2512A–AVR–04/02

• Bit2–PE:ParityError

Thisbit isset if thenext character in the receive bufferhad aParityErrorwhen received

and the paritychecking was enabled at that point (UPM1 = 1).Thisbit is valid until the

receive buffer(UDR) isread.Always set thisbit to zero when writing to UCSRA.

• Bit1–U2X: Double the USART Transmission Speed

Thisbit only has effect for theasynchronous operation. Write thisbit to zero when using

synchronous operation.

Writing thisbit to one will reducethe divisor of the baudrate dividerfrom 16 to 8 effec-

tively doubling thetransferrate for asynchronouscommunication.

• Bit 0 – MPCM: Multi-processor Communication Mode

Thisbit enables the Multi-processorCommunication mode. When the MPCM bit iswrit-

tentoone, all theincoming framesreceivedbythe USART Receiver that donotcontain

address information will beignored.TheTransmitter is unaffectedbythe MPCM setting.

For more detailed information see “Multi-processorCommunication Mode” on page 147.

USART Control and Status

• Bit7–RXCIE: RX Complete Interrupt Enable

Writing thisbit to one enables interruptontheRXC flag. A USART Receive Complete

interrupt will be generated only if theRXCIE bit iswrittentoone, the GlobalInterrupt

Flag in SREG iswritten to one and theRXC bit in UCSRA isset.

• Bit6–TXCIE: TX Complete Interrupt Enable

Writing thisbit to one enables interruptontheTXC flag. A USART Transmit Complete

interrupt will be generated only if theTXCIE bit iswrittentoone, the GlobalInterrupt

Flag in SREG iswritten to one and theTXC bit in UCSRA isset.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing thisbit to one enables interruptonthe UDREflag. A Data RegisterEmpty inter-

rupt will be generated only if the UDRIE bit iswritten to one, the GlobalInterrupt Flag in

SREG iswritten to one and the UDREbit in UCSRA isset.

• Bit4–RXEN: Receiver Enable

Writing thisbit to one enables the USART receiver.TheReceiverwill overridenormal

portoperation for theRxD pin when enabled. Disabling theReceiverwill flush the

receive buffer invalidating the FE, DOR, and PEflags.

• Bit3–TXEN: Transmitter Enable

Writing thisbit to one enables the USART Transmitter.TheTransmitterwill overridenor-

malportoperation for theTxD pin when enabled.The disabling of theTransmitter

(writing TXEN to zero)will not become effective until ongoing andpending transmis-

sions are completed. For example,when theTransmit ShiftRegister and Transmit

Bit 76543 210

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W RR/W

Initial Value00000000

1 2 ... 147 148 149 150 151 152 153 154 155 156 157 ... 222 223

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